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Junior Design Engineer Jobs in San Ramon, CA (NOW HIRING)

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$133K - $192K/yr

About the Role We are seeking a Physical Design Engineer to join our Silicon Engineering and ... Mentor junior engineers and provide technical guidance on physical implementation best practices.

Support Revolution

Hardware Design Engineer

San Jose, CA · On-site

$133 - $180/hr

We are seeking a Hardware Design Engineer to join our talented design team. In this role, you will ... Offer technical mentorship and guidance to junior engineers within the team * Perform other duties ...

Pacific Fusion

Mechanical Design Engineer

San Leandro, CA · On-site

$138K - $263K/yr

Mentor and support junior engineers on design and integration challenges Qualifications: * Bachelor's or Master's degree in Mechanical, Aerospace, or a related engineering field, or equivalent ...

Super Micro Computer

Hardware Design Engineer

San Jose, CA · On-site

$148K - $165K/yr

We are seeking a Hardware Design Engineer to join our talented design team. In this role, you will ... Offer technical mentorship and guidance to junior engineers within the team * Perform other duties ...

Orbotech

Sr. Mechanical Design Engineer

Milpitas, CA

$104K - $144K/yr

Mentor junior engineers and establish engineering best practices. * Support product roadmap ... Extensive knowledge of UHV system design, vacuum hardware, contamination control, and vacuum ...

KLA Corporation

Sr. Mechanical Design Engineer

Milpitas, CA · On-site

$104K - $144K/yr

Mentor junior engineers and establish engineering best practices. * Support product roadmap ... Extensive knowledge of UHV system design, vacuum hardware, contamination control, and vacuum ...

KLA

Sr. Mechanical Design Engineer

Milpitas, CA · On-site

$102K - $141K/yr

Mentor junior engineers and establish engineering best practices. * Support product roadmap ... Extensive knowledge of UHV system design, vacuum hardware, contamination control, and vacuum ...

Archer

Staff Design Engineer

San Jose, CA · On-site

$172K - $225K/yr

Provide technical guidance and mentorship to junior engineers * Interface with cross-functional groups including propulsion unit design, manufacturing, aerodynamics, and development test teams

Socket.dev

Packaging Design Engineer

San Jose, CA · On-site

$140 - $190/hr

... package design engineer. As a key member of the Package group, you will work across chip ... Mentor junior package designers in the group. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree ...

New

Pacific Fusion

Mechanical Design Engineer

San Leandro, CA · On-site

$138K - $263K/yr

Mentor and support junior engineers on design and integration challenges Qualifications: * Bachelor's or Master's degree in Mechanical, Aerospace, or a related engineering field, or equivalent ...

Pacific Fusion

Mechanical Design Engineer

Fremont, CA · On-site

$138K - $207K/yr

Mentor and support junior engineers on design and integration challenges * Interact with suppliers of vacuum systems components and electrical testing components for purchasing What You Bring

BotBot

Founding Design Engineer

San Francisco, CA · On-site

$165 - $210/hr

The junior/senior divide is gone on purpose; the expectations below describe how you work, not how ... design-minded engineer whose work shows genuine design depth. The center of gravity is design: we ...

New

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Showing results 21-40

All JobsDesign Engineer JobsJunior Design Engineer JobsJunior Design Engineer Jobs in San Ramon, CA

Junior Design Engineer information

See San Ramon, CA salary details

$37.4K

$80.2K

$122.4K

How much do junior design engineer jobs pay per year?

As of Sep 2, 2026, the average yearly pay for junior design engineer in San Ramon, CA is $80,237.00, according to ZipRecruiter salary data. Most workers in this role earn between $54,200.00 and $89,400.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a junior design engineer?

To thrive as a Junior Design Engineer, you need a solid background in engineering principles, problem-solving abilities, and typically a bachelor's degree in mechanical, electrical, or related engineering field. Familiarity with CAD software (such as AutoCAD or SolidWorks), simulation tools, and basic knowledge of manufacturing processes are commonly required. Strong attention to detail, effective communication, and a collaborative mindset help you excel in team settings and adapt to project needs. These skills ensure accurate design work, efficient project collaboration, and successful development of innovative engineering solutions.

What are some common challenges faced by junior design engineers during their first year, and how can they overcome them?

Junior Design Engineers often encounter challenges such as adapting to company-specific design processes, managing multiple project deadlines, and bridging the gap between theoretical knowledge and practical application. Building strong communication with senior engineers and actively seeking feedback can help address these hurdles. Participating in team meetings and collaborating closely with other departments, such as manufacturing or quality assurance, also enhances understanding and ensures smoother project execution. Embracing continuous learning and leveraging available training resources will further boost confidence and technical growth in the role.

What is the difference between Junior Design Engineer vs Mechanical Design Engineer?

AspectJunior Design EngineerMechanical Design Engineer
Required CredentialsBachelor's degree in engineering or related field; internships or entry-level certificationsBachelor's or higher in mechanical engineering; professional certifications optional
Work EnvironmentDesign teams, engineering firms, manufacturing companiesDesign departments, R&D labs, manufacturing industries
Employer & Industry UsageEntry-level roles in engineering firms, manufacturing, automotive, aerospaceMid to senior-level roles in similar industries, often with more project responsibility

The main difference is that a Junior Design Engineer is an entry-level position focusing on learning and supporting design tasks, while a Mechanical Design Engineer typically has more experience and responsibility in designing mechanical systems. Both roles require similar educational backgrounds, but the Mechanical Design Engineer usually has more advanced skills and project ownership.

Are junior design engineers well paid?

Junior design engineers typically earn entry-level salaries that vary by industry and location but generally range from $50,000 to $70,000 annually. Compensation can increase with experience, additional skills such as CAD proficiency, and relevant certifications. Entry-level roles often include opportunities for professional development and skill-building in design software and engineering principles.

What is the role of a junior design engineer?

A junior design engineer assists in developing and modifying engineering designs, often using CAD software, under the supervision of senior engineers. They support project planning, perform calculations, and help ensure designs meet specifications and standards. This role typically requires basic engineering knowledge, attention to detail, and good communication skills.

What are the most commonly searched types of Design Engineer jobs in San Ramon, CA?

The most popular types of Design Engineer jobs in San Ramon, CA are:

What cities near San Ramon, CA are hiring for Junior Design Engineer jobs?

Cities near San Ramon, CA with the most Junior Design Engineer job openings:

Junior Design Engineer jobs near you
Infographic showing various Junior Design Engineer job openings in San Ramon, CA as of July 2026, with employment types broken down into 84% Full Time, 13% Part Time, and 3% Contract. Highlights an 83% Physical, 4% Hybrid, and 13% Remote job distribution, with an average salary of $80,237 per year, or $38.6 per hour.

Physical Design Engineer

Altera Corporation

San Jose, CA • On-site

$133K - $192K/yr

Full-time

Re-posted 23 days ago

Job description

Job Details:
Job Description:
About Altera
At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
We are seeking a Physical Design Engineer to join our Silicon Engineering and Physical Design organization. In this role, you will be responsible for implementing advanced custom IP and SoC designs from RTL through GDSII while driving timing closure, power optimization, physical verification, and design signoff for leading-edge semiconductor products. You will work closely with architecture, RTL, DFT, synthesis, verification, and methodology teams to deliver high-quality silicon for next-generation FPGA technologies.
Key Responsibilities
  • Perform full-chip and block-level physical design implementation of custom IP and SoC designs from RTL through GDSII, delivering manufacturing-ready design databases.
  • Execute all stages of the physical design flow, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing closure, and physical optimization.
  • Perform static timing analysis (STA) and resolve setup, hold, signal integrity, and timing violations to achieve design closure.
  • Develop and optimize clock distribution networks, power distribution networks, and multiple power domain implementations to meet performance, power, and reliability targets.
  • Conduct physical verification and signoff activities, including formal equivalence checking (LEC), static timing analysis, power integrity, IR drop, electromigration (EM), layout verification, electrical rule checking (ERC), design rule checking (DRC), layout versus schematic (LVS), and structural verification.
  • Analyze physical design results and identify root causes of implementation issues while driving corrective actions to improve current and future product architectures.
  • Optimize physical implementations to improve product-level metrics including performance, power consumption, frequency, area (PPA), manufacturability, and reliability.
  • Collaborate closely with RTL, Logic Design, DFT, CAD, Architecture, Verification, and Product Engineering teams throughout the design cycle.
  • Support Design-for-Test (DFT) integration and implementation throughout physical design and signoff.
  • Drive physical design convergence across multiple design iterations while balancing timing, power, congestion, and area tradeoffs.
  • Contribute to the development, enhancement, and automation of physical design methodologies, flows, and infrastructure.
  • Mentor junior engineers and provide technical guidance on physical implementation best practices.

What You'll Bring
  • Strong understanding of modern semiconductor physical implementation methodologies.
  • Excellent analytical and debugging skills for solving complex timing, congestion, and physical implementation challenges.
  • Ability to balance power, performance, and area tradeoffs across large-scale SoC designs.
  • Strong communication skills with the ability to collaborate effectively across multidisciplinary engineering teams.
  • Passion for building high-quality silicon and continuously improving engineering methodologies.

Why Join Altera?
At Altera, you'll help shape the future of programmable computing while working alongside some of the industry's most accomplished semiconductor engineers. We offer challenging technical problems, opportunities to influence next-generation FPGA products, competitive compensation, comprehensive benefits, and long-term wealth-building opportunities through our equity programs. If you're passionate about delivering world-class silicon and advancing physical design methodologies, we'd love to hear from you.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$133,200 - $192,825 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#LI-MD1
Qualifications:
Minimum Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline and 5+ years of experience in semiconductor Physical Design.
  • 5+ years of experience implementing custom IP or SoC designs from RTL through GDSII.
  • 5+ years of experience with physical design flows including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and physical optimization.
  • 3+ years of experience performing static timing analysis (STA) and achieving timing closure on advanced semiconductor designs.
  • 3+ years of experience with physical verification and signoff, including DRC, LVS, ERC, LEC, IR drop, electromigration (EM), and power integrity analysis.

Preferred Qualifications
  • Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • Experience with advanced technology nodes (7nm, 5nm, 3nm, or smaller).
  • Experience implementing high-performance CPU, FPGA, AI accelerator, networking, or SoC designs.
  • Experience with Tcl, Python, Perl, or Shell scripting for flow automation.
  • Knowledge of static timing analysis, low-power implementation methodologies including UPF/CPF.

Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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