Perform firmware debugging using JTAG/SWD, oscilloscopes, logic analyzers, and other debugging tools. * Troubleshoot hardware/firmware integration issues. * Optimize firmware for performance, memory ...
Perform firmware debugging using JTAG/SWD, oscilloscopes, logic analyzers, and other debugging tools. * Troubleshoot hardware/firmware integration issues. * Optimize firmware for performance, memory ...
Embedded Firmware Senior Engineer
$120K - $159K/yr
Proficient in debugging embedded systems using JTAG/SWD debuggers, oscilloscopes, logic analyzers, and protocol analyzers. * Proven ability to apply principles of logical and scientific thinking to ...
Embedded Firmware Senior Engineer
$120K - $159K/yr
Proficient in debugging embedded systems using JTAG/SWD debuggers, oscilloscopes, logic analyzers, and protocol analyzers. * Proven ability to apply principles of logical and scientific thinking to ...
SoC Debug Engineer
San Diego, CA · On-site
$140K - $210K/yr
Experience with debug tools such as JTAG. * Proficiency using lab equipment (logic analyzer, oscilloscope, signal generator, etc.). * Bachelor's degree in Science, Engineering, or related field and ...
SoC Debug Engineer
San Diego, CA · On-site
$140K - $210K/yr
Experience with debug tools such as JTAG. * Proficiency using lab equipment (logic analyzer, oscilloscope, signal generator, etc.). * Bachelor's degree in Science, Engineering, or related field and ...
Embedded Firmware Senior Engineer - Alliance Laundry
Ripon, WI · On-site
$125 - $150/hr
... and JTAG/debug probes. Partner with suppliers and in-house teams to refine and optimize embedded subsystems, components, and third-party firmware modules. Ensure firmware meets marketing ...
Embedded Firmware Senior Engineer - Alliance Laundry
Ripon, WI · On-site
$125 - $150/hr
... and JTAG/debug probes. Partner with suppliers and in-house teams to refine and optimize embedded subsystems, components, and third-party firmware modules. Ensure firmware meets marketing ...
DFT Engineer
Santa Clara, CA · On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
DFT Engineer
Santa Clara, CA · On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
Embedded Firmware Senior Engineer
Ripon, WI · On-site
$120K - $159K/yr
Proficient in debugging embedded systems using JTAG/SWD debuggers, oscilloscopes, logic analyzers, and protocol analyzers. * Proven ability to apply principles of logical and scientific thinking to ...
Embedded Firmware Senior Engineer
Ripon, WI · On-site
$120K - $159K/yr
Proficient in debugging embedded systems using JTAG/SWD debuggers, oscilloscopes, logic analyzers, and protocol analyzers. * Proven ability to apply principles of logical and scientific thinking to ...
Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug * Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools * Strong background in scan insertion ...
Quick apply
Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug * Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools * Strong background in scan insertion ...
JTAG * GDB * Embedded debugging tools * Develop and maintain device drivers for peripheral interfaces such as UART, SPI, and I2C. * Collaborate with cross-functional engineering teams to resolve ...
JTAG * GDB * Embedded debugging tools * Develop and maintain device drivers for peripheral interfaces such as UART, SPI, and I2C. * Collaborate with cross-functional engineering teams to resolve ...
ASIC DFT Engineer
Plano, TX · Remote
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
ASIC DFT Engineer
Plano, TX · Remote
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
DFx Verification Engineer
Santa Clara, CA · On-site
$158K/yr
ATPG pattern validation and debug * BIST controllers and memory test logic Technical Skills * Strong knowledge of: * DFT concepts (Scan, ATPG, MBIST, JTAG) * Digital design fundamentals * Expertise ...
DFx Verification Engineer
Santa Clara, CA · On-site
$158K/yr
ATPG pattern validation and debug * BIST controllers and memory test logic Technical Skills * Strong knowledge of: * DFT concepts (Scan, ATPG, MBIST, JTAG) * Digital design fundamentals * Expertise ...
Lead ASIC DFT Engineer
San Jose, CA · On-site
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
Lead ASIC DFT Engineer
San Jose, CA · On-site
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Lead ASIC DFT Engineer
San Jose, CA · On-site
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
Lead ASIC DFT Engineer
San Jose, CA · On-site
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Lead ASIC DFT Engineer
San Jose, CA · Remote
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
Lead ASIC DFT Engineer
San Jose, CA · Remote
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Lead ASIC DFT Engineer
Plano, TX · Remote
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
Lead ASIC DFT Engineer
Plano, TX · Remote
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug. * Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. * Proven experience in ...
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug. * Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools. * Proven experience in ...
TEMP Principal DevOps Engineer
Marlborough, MA · On-site
$85/hr
Threat models must cover information flows, trust boundaries, data stores, external entities, comms protocols, externally accessible physical/debug ports, JTAG/debug headers and hardware attack ...
TEMP Principal DevOps Engineer
Marlborough, MA · On-site
$85/hr
Threat models must cover information flows, trust boundaries, data stores, external entities, comms protocols, externally accessible physical/debug ports, JTAG/debug headers and hardware attack ...
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
ASIC DFT Engineer
Irvine, CA · On-site
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
ASIC DFT Engineer
Irvine, CA · On-site
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Quick apply
Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. * Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL ...
Jtag Debugger information
See salary details
$8.41 - $9.35
3% of jobs
$9.35 - $10.29
5% of jobs
$10.29 - $11.23
6% of jobs
$11.23 - $12.17
5% of jobs
$12.67 is the 25th percentile. Wages below this are outliers.
$12.17 - $13.11
9% of jobs
$13.11 - $14.05
7% of jobs
$14.05 - $14.99
13% of jobs
The median wage is $15.02 / hr.
$14.99 - $15.93
17% of jobs
$16.53 is the 75th percentile. Wages above this are outliers.
$15.93 - $16.87
14% of jobs
$16.87 - $17.81
12% of jobs
$17.81 - $18.75
8% of jobs
$8
$14
$18
How much do jtag debugger jobs pay per hour?
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For Jtag Debugger jobs, the most frequently searched job titles are:

Bare Metal Firmware Engineer
Sunnyvale, CA • On-site
Other
Posted 17 days ago
Job description
-
Role: Bare Metal Firmware Engineer
Job Summary:
We are looking for a skilled Bare Metal Firmware Engineer with experience in developing and debugging low-level firmware for embedded systems. The candidate will be responsible for writing firmware that runs directly on microcontrollers/SoCs without an operating system.
Key Responsibilities:
- Develop and maintain bare-metal firmware for embedded systems.
- Work with C/C++ for low-level firmware development.
- Develop and debug drivers for GPIO, UART, SPI, I2C, I2S, PWM, ADC/DAC, etc.
- Work closely with hardware teams to understand schematics and hardware interfaces.
- Perform firmware debugging using JTAG/SWD, oscilloscopes, logic analyzers, and other debugging tools.
- Troubleshoot hardware/firmware integration issues.
- Optimize firmware for performance, memory usage, and reliability.
- Participate in code reviews, testing, and documentation.
Basic Qualifications:
- 3+ years of experience in Embedded Firmware / Bare Metal Firmware development.
- Strong programming skills in C/C++.
- Good understanding of microcontrollers, processors, memory, interrupts, timers, and peripherals.
- Experience with ARM-based microcontrollers/SoCs is preferred.
- Experience with firmware debugging and hardware bring-up.
- Good understanding of embedded systems and hardware/software interaction.
Preferred Skills:
- ARM Cortex-M / Cortex-A
- Embedded Linux knowledge is a plus
- RTOS experience is a plus
- JTAG/SWD debugging
- Git and embedded development tools
- Experience with board bring-up and device drivers
About Info Way Solutions
Sourced by ZipRecruiter
Industry
It services
Company size
51 - 200 Employees
Headquarters location
Fremont, CA, US
Year founded
2012