Link Layer architect
Santa Clara, CA ยท On-site
Define and develop link layer architectures forvarioushigh-speed interconnects (Ethernetand custom link-layers) * Drive link layer architecture in the context of full-system performance, power ...
Santa Clara, CA ยท On-site
Define and develop link layer architectures forvarioushigh-speed interconnects (Ethernetand custom link-layers) * Drive link layer architecture in the context of full-system performance, power ...
Santa Clara, CA ยท On-site
Define and develop link layer architectures forvarioushigh-speed interconnects (Ethernetand custom link-layers) * Drive link layer architecture in the context of full-system performance, power ...
Santa Clara, CA ยท On-site
Drive link layer architecture in the context of full-system performance, power, reliability and scalability goals * Create architectural specifications and design documents for link layer protocols ...
Santa Clara, CA ยท On-site
Drive link layer architecture in the context of full-system performance, power, reliability and scalability goals * Create architectural specifications and design documents for link layer protocols ...
San Francisco, CA ยท On-site
$152K - $196K/yr
About the team Link is one of the fastest-growing consumer networks in the world, with 300M+ registered consumers. Our core mission is to make commerce seamless, helping merchants drive material ...
San Francisco, CA ยท On-site
$152K - $196K/yr
About the team Link is one of the fastest-growing consumer networks in the world, with 300M+ registered consumers. Our core mission is to make commerce seamless, helping merchants drive material ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
The Data Link subsystems team develops the next generation of high capacity, covert, and agile data links. From space based to terrestrial RF links, Raytheon develops RF data link subsystems for the ...
The Data Link subsystems team develops the next generation of high capacity, covert, and agile data links. From space based to terrestrial RF links, Raytheon develops RF data link subsystems for the ...
The Data Link subsystems team develops the next generation of high capacity, covert, and agile data links. From space based to terrestrial RF links, Raytheon develops RF data link subsystems for the ...
The Data Link subsystems team develops the next generation of high capacity, covert, and agile data links. From space based to terrestrial RF links, Raytheon develops RF data link subsystems for the ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
The Data Link subsystems team develops the next generation of high capacity, covert, and agile data links. From space based to terrestrial RF links, Raytheon develops RF data link subsystems for the ...
The Data Link subsystems team develops the next generation of high capacity, covert, and agile data links. From space based to terrestrial RF links, Raytheon develops RF data link subsystems for the ...
$189K - $271K/yr
Lead link budget analysis, channel modeling, and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rate (BER) across transmit and receive paths. * Define and optimize ...
$189K - $271K/yr
Lead link budget analysis, channel modeling, and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rate (BER) across transmit and receive paths. * Define and optimize ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Carlsbad, CA ยท On-site
$189K - $271K/yr
Lead link budget analysis, channel modeling, and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rate (BER) across transmit and receive paths. * Define and optimize ...
Carlsbad, CA ยท On-site
$189K - $271K/yr
Lead link budget analysis, channel modeling, and statistical simulations to evaluate jitter, noise, crosstalk, and bit error rate (BER) across transmit and receive paths. * Define and optimize ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Data link hardware development * Algorithm development * Digital signal processing What You Will Do * Perform and/or evaluate concept and performance trade studies, link budget analyses and ...
Santa Rosa, CA ยท On-site
$23.30 - $28.32/hr
As a Job Link Intern with the County of Sonoma, you will perform a variety of administrative and clerical activities, such as: creating, updating, and closing client case files (physical and/or ...
Santa Rosa, CA ยท On-site
$23.30 - $28.32/hr
As a Job Link Intern with the County of Sonoma, you will perform a variety of administrative and clerical activities, such as: creating, updating, and closing client case files (physical and/or ...
Santa Rosa, CA ยท On-site
$23.30 - $28.32/hr
As a Job Link Intern with the County of Sonoma, you will perform a variety of administrative and clerical activities, such as: creating, updating, and closing client case files (physical and/or ...
Santa Rosa, CA ยท On-site
$23.30 - $28.32/hr
As a Job Link Intern with the County of Sonoma, you will perform a variety of administrative and clerical activities, such as: creating, updating, and closing client case files (physical and/or ...
San Jose, CA ยท On-site
$190K - $223K/yr
Sr. Staff Engineer, Electrical Link Architecture Location: San Jose, CA (on-site) Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co ...
San Jose, CA ยท On-site
$190K - $223K/yr
Sr. Staff Engineer, Electrical Link Architecture Location: San Jose, CA (on-site) Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co ...
San Jose, CA ยท On-site
$180K - $230K/yr
Sr. Staff Engineer, Electrical Link Architecture Location: San Jose, CA (on-site) Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co ...
San Jose, CA ยท On-site
$180K - $230K/yr
Sr. Staff Engineer, Electrical Link Architecture Location: San Jose, CA (on-site) Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co ...
Camp Pendleton, CA ยท On-site
$115K - $120K/yr
Auria is looking to hire a Tactical Data Link (TDL) Analyst. This role is ONSITE at Camp Pendleton, CA. This is currently a contingent position and requires an active Secret security clearance. The ...
Camp Pendleton, CA ยท On-site
$115K - $120K/yr
Auria is looking to hire a Tactical Data Link (TDL) Analyst. This role is ONSITE at Camp Pendleton, CA. This is currently a contingent position and requires an active Secret security clearance. The ...
Own link budget and verification methodology while staying hands-on with the validating measurements * Characterize eye diagrams, BER, jitter, equalization, and channel impairments * Support silicon ...
Own link budget and verification methodology while staying hands-on with the validating measurements * Characterize eye diagrams, BER, jitter, equalization, and channel impairments * Support silicon ...
| Aspect | Job Link | Job Coordinator |
|---|---|---|
| Required Credentials | High school diploma or equivalent; some roles may require certifications | High school diploma; certifications may be preferred |
| Work Environment | Office settings, online platforms, recruitment agencies | Office environments, client sites, event locations |
| Employer & Industry Usage | Recruitment firms, staffing agencies, HR departments | HR departments, staffing agencies, project teams |
| Common Search & Comparison | Yes | Yes |
Job Link and Job Coordinator roles often overlap in recruitment and staffing industries. Job Link typically refers to online job postings or platforms connecting employers and candidates, while Job Coordinator involves managing recruitment processes, scheduling interviews, and coordinating candidate activities. Both roles require communication skills and organizational abilities, but Job Link focuses more on digital platforms, whereas Job Coordinator emphasizes direct interaction and logistics management.

Full-time
Life, Retirement
Re-posted 14 days ago
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell's Compute and Custom Solutions organization (CCS) is looking for a talented senior ASIC link layer architect to join our architecture team. This team acts as the central technical interface to our datacenter clients. It is responsible for the overall technology choice, silicon partitioning strategy, IP definition and selection and architectural guidance of datacenter products (SmartNIC, servers, AI accelerators and switches, mainly) for the main hyperscalers and companies worldwide. We actively participate in the definition of next generation datacenter products with our clients and respond to their ASIC RFQs. Role spans engagement with both customers and internal technology teams to define the best solution to the custom product needs and includes all functions required to build, test and manufacture an advanced custom silicon System in a Package.What You Can Expect
We are seeking a senior Link Layer Architect to own the end-to-end architecture of link layer solutions across high-speed interconnect protocols including Ethernet,Custom link-layersand Die-to-Die (D2D) interfaces.
This role offers the opportunity to shape the future of high-speed interconnect technologies at Marvell,engagingwith customers toenablenext-generation computing and communication systemsas an integralpart of theCustom Solutions Architecture team.
Architecture & Technical Leadership
Define and develop link layer architectures forvarioushigh-speed interconnects (Ethernetand custom link-layers)
Drive link layer architecture in the context of full-system performance, power,reliabilityand scalability goals
Create architectural specifications and design documents for link layer protocols and implementations
Drive technical decisions on link layer features including error correction, flow control, retry mechanisms, and data integrity
Evaluate and recommend new link layer technologies and standards for next-generation productsand custom solutions
Lead architecture reviews andprovidetechnical guidance to cross-functional teams
System Integration & Optimization
Define interfaces between link layer, transaction layer, and physical layer
Optimizelink efficiency, latency, and bandwidthutilization
Standards & Industry Engagement
Stay current with emerging link layer standards and technologies
Contribute to specification development and review
Ensure compliance with industry standards and specifications
Cross-Functional Collaboration
Engage directly with customersonarchitecture discussions, including requirements definition, architectural alignment, and design trade-offs
Work closely with PHY architects, system architects, and ASIC design teams
Partner with verification teams to define test plans and coverage strategies
Support hardware bring-up and validation teams with technicalexpertise
Innovation & Technology Development
Research and evaluate new link layer technologies and approaches
Develop proof-of-concept implementations for novel link layer features
Create reusable IP blocks and architectural frameworks
Drive continuous improvement in link layer performance and reliability
Documentation & Knowledge Sharing
Create comprehensive architecture specifications and design documentation
Develop datasheets, integration guides, and reference designs
Present technical concepts to internal teams and external customers
Mentor engineers and share link layerexpertiseacross the organization
What We're Looking For
Technical Expertise
Extensive experience (typically 10+ years) in link-layer design and architecture
Deep understanding of Ethernet link layerIEEE 802.3(100Gand 200G)
Strong knowledge of link layer protocols, error detection/correction, and reliability mechanisms
Experience with FEC implementations (Reed-Solomon, Hamming, BCH, etc.)
Understanding of link training, equalization, and physical layer interaction
Architecture Skills
Proventrack recordof defining successful system architectures
Experience guiding RTL design and verification, including design reviews and architectural trade-offs (hands-on experience a plus)
Understanding of SerDes/PHY interfaces and requirements
Communication & Leadership
Excellent written and verbal communication skills
Ability to present complex technical concepts to diverse audiences
Experience leading cross-functional technical initiatives
Strong problem-solving and analytical capabilities
Preferred Qualifications
MS or PhD in Electrical Engineering, Computer Engineering, or related field
Experience with chiplet architectures and advanced packaging
Prior involvement in industry standards organizations
Knowledge of network protocol stacks and system architecture
Key Competencies
Strategic thinking and long-term technology planning
Innovation and creative problem-solving
Collaborative and team-oriented approach
Customer focus and business acumen
Adaptability to emerging technologies
Attention to detail and quality
Expected Base Pay Range (USD)
191,530 - 286,900, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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Manufacturing
10,000+ Employees
Santa Clara, CA, US
1995