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Internship Target Designer Jobs in California (NOW HIRING)

Intel

Mixed Signal Logic Design Engineer

San Jose, CA

$122K - $232K/yr

Applies various strategies, tools, and methods for mixed signal designs including analog behavior ... experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications:

Axos Bank

Automation Analyst Intern

San Diego, CA · On-site

$20 - $25/hr

Axos Bank Target Range: $20.00 - $25.00 Actual starting pay will vary based on factors including ... Interns have a choice between one of two sessions to accommodate varying school calendars. Session ...

Axos Bank

Automation Analyst Intern

San Diego, CA

$20 - $25/hr

Axos Bank Target Range: $20.00 - $25.00 Actual starting pay will vary based on factors including ... Interns have a choice between one of two sessions to accommodate varying school calendars. Session ...

Aerotek

Sales Development Representative

Emeryville, CA · On-site

The Sales Development Representative must identify target accounts in defined territory and make ... This entry-level sales role is designed for individuals eager to learn the full sales cycle, with a ...

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Mixed Signal Logic Design Engineer

Intel

San Jose, CA

$122K - $232K/yr

Full-time

Medical, Retirement, PTO

Re-posted 10 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Job Details:Job Description: 

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

  • Bachelors with 4+ years of experience or master's with 3+ years of experience or PhD with 1+ years of experience in Computer Science or Computer Engineering or Electrical Engineering or related technical discipline

2+ years of experience with the following technical skills:

  • Proficiency in RTL design and coding using System Verilog and Verilog.
  • Expertise in mixed signal fundamentals, low-power design using UPF, and clock gating.
  • Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs.
  • Experience with hardware simulation tools and methodologies (VCS/Verdi). - Familiarity with IP environment and configuration management tools
  • Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low power design.

This position is not eligible for an intel immigration sponsorship.

Preferred Qualifications:

  • Demonstrated ability to debug complex logic designs, speed paths and validate system-level functionality.
  • Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic team environment.
  • Strong problem-solving skills, disciplined execution, and a proactive mindset.
  • DDR Design domain knowledge with good hold on DFI/DDR/LPDDR protocols
  • VSCode GitHub CoPilot or any other AI experience.- Exposed to Formal Property Verification and Git version control
  • Ability to drive an optimal solution between analog and digital designs
  • Familiarity with pre-silicon and post-silicon validation.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, FolsomAdditional Locations:US, California, San Jose, US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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