1

Internship Marriott Global Design Jobs in Phoenix, AZ

By submitting your interest, you'll be among the first to know when internship opportunities open ... Participating on an Agile Scrum team, collaborating across design, development, and testing

By submitting your interest, you'll be among the first to know when internship opportunities open ... Participating on an Agile Scrum team, collaborating across design, development, and testing

By submitting your interest, you'll be among the first to know when internship opportunities open ... Participating on an Agile Scrum team, collaborating across design, development, and testing

By submitting your interest, you'll be among the first to know when internship opportunities open ... Participating on an Agile Scrum team, collaborating across design, development, and testing

UIUX Internship

Scottsdale, AZ · On-site +1

$15.25 - $20.25/hr

Overview We are seeking a UX Design Intern to transform complex, technical enterprise products into ... With a presence in 100 countries, 11,000+ customers, and a global team of over 1,400+ passionate ...

UIUX Internship

Scottsdale, AZ · On-site +1

$15 - $20/hr

Overview We are seeking a UX Design Intern to transform complex, technical enterprise products into ... With a presence in 100 countries, 11,000+ customers, and a global team of over 1,400+ passionate ...

UIUX Internship

Scottsdale, AZ · On-site +1

$15 - $20/hr

We are seeking a UX Design Intern to transform complex, technical enterprise products into simple ... With a presence in 100 countries, 11,000+ customers, and a global team of over 1,400+ passionate ...

The internship program will run from Monday, June 1, through Wednesday, August 5 . Interns must be ... Coursework or project experience in Human-Centered Design, journey mapping, service design, or UX ...

next page

Showing results 1-20

Internship Marriott Global Design information

See Phoenix, AZ salary details

$9

$19

$36

How much do internship marriott global design jobs pay per hour?

As of May 28, 2026, the average hourly pay for internship marriott global design in Phoenix, AZ is $19.24, according to ZipRecruiter salary data. Most workers in this role earn between $14.33 and $21.49 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Internship Marriott Global Design, and why are they important?

To thrive as an intern at Marriott Global Design, you typically need a background in architecture, interior design, or a related field, along with strong project management and organizational skills. Familiarity with design software such as AutoCAD, Revit, SketchUp, and Adobe Creative Suite is usually required. Creativity, attention to detail, strong communication, and teamwork abilities help interns contribute effectively to design projects. These skills and qualities are crucial for supporting innovative, high-quality hospitality design while collaborating within a global team environment.

What types of projects and responsibilities can I expect during an internship with Marriott Global Design?

As an intern with Marriott Global Design, you can expect to work on a variety of projects that may include assisting with the development of hotel design concepts, supporting project documentation, conducting research on design trends, and collaborating with architects and designers on both new builds and renovations. Interns often participate in team meetings, help prepare presentations, and interact with other departments such as procurement and operations. This hands-on experience is designed to give you exposure to the full design process in a dynamic, collaborative environment, helping you build a strong foundation for a career in hospitality design.

What is an Internship at Marriott Global Design?

An Internship at Marriott Global Design is a temporary position designed for students or recent graduates interested in gaining hands-on experience in hospitality design. Interns typically work alongside experienced professionals on real-world projects related to architecture, interior design, and brand development for Marriott's hotel properties worldwide. The internship provides exposure to the design process, industry standards, and Marriott's unique approach to creating guest experiences. It is an opportunity to learn, develop relevant skills, and explore potential career paths within the hospitality design sector.

What is the difference between Internship Marriott Global Design vs Internship Marriott Hotel Operations?

AspectInternship Marriott Global DesignInternship Marriott Hotel Operations
FocusDesign, branding, and development of hotel interiors and aestheticsFront desk, guest services, and daily hotel management tasks
Required SkillsDesign software, creativity, industry knowledgeCustomer service, communication, operational skills
Work EnvironmentDesign studios, corporate offices, project sitesHotel properties, front desk, operational departments
Industry UsageDesign and branding teams within MarriottHotel management and guest services teams

Internship Marriott Global Design focuses on creative design and branding for Marriott hotels, involving interior design and project development. In contrast, Internship Marriott Hotel Operations emphasizes guest services and daily hotel management. Both internships provide valuable industry experience but target different skill sets and career paths within Marriott.

What cities near Phoenix, AZ are hiring for Internship Marriott Global Design jobs? Cities near Phoenix, AZ with the most Internship Marriott Global Design job openings:
SOC Physical Design Static Timing Analysis Engineer

SOC Physical Design Static Timing Analysis Engineer

Intel

Phoenix, AZ

$164.47K - $311.89K/yr

Full-time

Medical, Retirement, PTO

Posted 29 days ago


Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers


Job description

Job Details:Job Description: 

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.

Key Responsibilities:

  • Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
  • Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
  • Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
  • Define methodologies to produce high-quality timing models and enable efficient physical design execution.
  • Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
  • Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
  • Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
  • Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

  • Bachelor's degree with 8 +years or master's degree with 6+ years or PhD with 4+ years in Electrical Engineering or Computer Engineering or Computer Science or a related field.
  • 7+ years technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
  • 3+ years of experience with the following skills:
  • Strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques.
  • Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.

Preferred Skills/Experience:

  • Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
  • Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
  • Knowledge of tools, flows, and methodologies for high-performance physical design.
  • Strong communication skills and ability to articulate technical concepts effectively.
  • DFT architecture knowledge is a strong plus
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa ClaraBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


Intel logo

About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968