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Internship Formal Verification Engineer Jobs in Oregon

Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...

Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...

Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...

You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...

You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...

You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...

RTL Design Engineer

Beaverton, OR · On-site

$120 - $180/hr

You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Formal verification and low-power design methodologies * Hardware-software co-design and system ...

Showing results 41-60

Internship Formal Verification Engineer information

What is the difference between Internship Formal Verification Engineer vs Formal Verification Engineer?

AspectInternship Formal Verification EngineerFormal Verification Engineer
QualificationsEnrolled in or recent graduate in Computer Engineering, Electrical Engineering, or related fieldsBachelor's or Master's in Electrical Engineering, Computer Science, or related fields; certifications are a plus
Work EnvironmentInternship programs, entry-level tasks, supervised projectsFull-time professional role, independent project work, team collaboration
Industry UsageCommon in semiconductor, electronics, and hardware companies for trainingEstablished role in hardware design, verification teams, and chip development

The main difference is that an Internship Formal Verification Engineer is a training position for students or recent graduates gaining initial experience, while a Formal Verification Engineer is a full-time professional responsible for verifying hardware designs independently. Interns focus on learning and assisting, whereas full engineers lead verification processes.

What are the most commonly searched types of Formal Verification Engineer jobs in Oregon?

The most popular types of Formal Verification Engineer jobs in Oregon are:

What are popular job titles related to Internship Formal Verification Engineer jobs in Oregon?

For Internship Formal Verification Engineer jobs in Oregon, the most frequently searched job titles are:

Infographic showing various Internship Formal Verification Engineer job openings in Oregon as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, 4% Contract, and 1% Nights. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution.

Digital Verification Engineer Lead (MTD, Tualatin, OR)

Teradyne

Tualatin, OR • On-site

$154K - $247K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 17 days ago


Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose  
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovate and learn something new every day. 
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. 
Opportunity Overview 

Act as a digital functional verification technical lead responsible for the planning, strategy, and execution of challenging FPGA verification projects. Provide technical leadership for large, cross-site verification teams. The position requires interfacing with other functional groups (e.g. hardware, software, applications).


All About You 
We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

  • Master's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 10 years of relevant work experience OR Bachelor's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 12 years of relevant work experience
  • Experience with verification planning and testbench architecture
  • Experience with complete functional verification cycle from Design Specification Review to verification closure
  • Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification
  • Expertise with UVM testbench development and Verification IP integration
  • Experience with Reference models development and integration
  • Knowledge of at least one of the following protocols/technologies: Ethernet, PCIe, AXI, MIPI, DRAM, FLASH
  • Experience with regression failures analysis
  • Experience with verification progress tracking
  • Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)
  • Experience working with revision source control (e.g. clearcase, git, svn)
  • Ability to track and bring issues to closure. Detailed oriented. Excellent planning and organizational skills.
  • Experience leading verification team
  • Experience working with teams located in different time zones
  • Experience mentoring junior engineers

Desired (but not required) skills/experience:

  • Experience in FPGA design implementation with System Verilog
  • Experience in verification of Automated Test Equipment functionality
  • Static and/or dynamic Formal Verification
  • Experience with GVP source control continuous integration tool

Compensation: 
The base salary range for this role is$154,900 - $247,800.This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. 

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits:Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details
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