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Internship Asic Rtl Design Engineer Jobs in Wilsonville, OR

Rambus

Hardware Design Engineer

Hillsboro, OR · On-site

$106K - $198K/yr

  • Medical

  • Dental

  • Retirement

RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$129K - $194K/yr

  • Medical

  • Dental

  • Retirement

Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$129K - $194K/yr

  • Medical

  • Dental

  • Retirement

Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$150K - $277K/yr

  • Medical

  • Dental

  • Retirement

Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...

Apple

FE RTL Infrastructure - CAD Engineer

Beaverton, OR

$150K - $277K/yr

  • Medical

  • Dental

  • Retirement

Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...

Intel

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $232K/yr

  • Medical

  • Retirement

  • PTO

Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

Apple

Timing Design Engineer

Beaverton, OR

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

Apple

Timing Design Engineer

Beaverton, OR

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Wilsonville, OR

Internship Asic Rtl Design Engineer information

See Wilsonville, OR salary details

$97.3K

$155.4K

$209K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for internship asic rtl design engineer in Wilsonville, OR is $155,399.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,100.00 and $186,200.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Wilsonville, OR?

For Internship Asic Rtl Design Engineer jobs in Wilsonville, OR, the most frequently searched job titles are:

Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Wilsonville, OR as of August 2026, with employment types broken down into 52% Full Time, 11% Part Time, and 37% Contract. Highlights an 100% In-person job distribution, with an average salary of $155,399 per year, or $74.7 per hour.

Hardware Design Engineer

Rambus

Hillsboro, OR • On-site

$106K - $198K/yr

Other

Medical, Dental, Retirement

Re-posted 28 days ago

Job description

Overview
Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional HW Design Engineer to join our MCG team in Hillsboro. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Responsibilities
  • Design architecting and trade-off analysis
  • RTL coding and verification
  • Memory Controller + PHY integration and verification
  • Customer delivery and support

Qualifications
Strong System Verilog/Verilog RTL design expertise
  • Questa/Incisive/VCS simulator experience
  • Python/Perl/Tcl scripting experience
  • Significant ASIC and/or FPGA design experience
  • Ability to learn quickly and work independently
  • Solid communication and project management skills
  • 5+ years of logic design experience
  • BSEE

Definite Plus:
  • ASIC synthesis, timing constraint, CDC/RDC experience
  • Verification experience
  • Memory (HBM, GDDR, LPDDR, DDR) expertise
  • AMBA AXI or CHI design experience
  • Located in the Hillsboro, Oregon area

Training:
  • Provided as needed

About Rambus
Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow's systems.
Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
The US salary range for this full-time position is $106,900 to $198,500. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard.
Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.
Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.
Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.
For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.
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