PHY RTL Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
PHY RTL Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description Develop signal processing intensive design for wireless communication SoCs ...
Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$175K - $225K/yr
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer who will report to the ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND ...
Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$175K - $225K/yr
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer who will report to the ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND ...
Principal ASIC Design Verification Engineer
$190K - $285K/yr
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ... Engineering, or related field. * 10+ years of experience in ASIC/SoC verification. * Solid ...
Quick apply
Principal ASIC Design Verification Engineer
$190K - $285K/yr
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ... Engineering, or related field. * 10+ years of experience in ASIC/SoC verification. * Solid ...
ASIC DFT Engineer
Irvine, CA · On-site
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...
Quick apply
ASIC DFT Engineer
Irvine, CA · On-site
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · Hybrid
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · Hybrid
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
FPGA Engineer with Security Clearance
El Segundo, CA · On-site
$131K - $180K/yr
... FPGA/ASIC digital architectures - RTL design and implementation in VHDL or Verilog - Timing ... Engineering, or related field - Expertise in FPGA design and/or verification - Strong VHDL ...
FPGA Engineer with Security Clearance
El Segundo, CA · On-site
$131K - $180K/yr
... FPGA/ASIC digital architectures - RTL design and implementation in VHDL or Verilog - Timing ... Engineering, or related field - Expertise in FPGA design and/or verification - Strong VHDL ...
Principal ASIC Design Engineer (Starshield)
$200K - $285K/yr
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...
Principal ASIC Design Engineer (Starshield)
$200K - $285K/yr
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...
Principal ASIC Physical Design Engineer
$190K - $280K/yr
You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Quick apply
Principal ASIC Physical Design Engineer
$190K - $280K/yr
You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
Sr. ASIC Design Engineer (Starshield)
$160K - $225K/yr
SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...
Sr. ASIC Design Engineer (Starshield)
$160K - $225K/yr
SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Duration ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...
Quick apply
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Duration ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...
Wireless RTL Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Wireless RTL Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...
Wireless RTL Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Wireless RTL Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Wireless RTL Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Wireless RTL Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Sr. ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$160K - $225K/yr
As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...
Sr. ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$160K - $225K/yr
As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...
Principal Digital Design Engineer
Irvine, CA · On-site
$190K - $225K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
Principal Digital Design Engineer
Irvine, CA · On-site
$190K - $225K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
Internship Asic Rtl Design Engineer information
See Long Beach, CA salary details
$98.8K - $109.2K
16% of jobs
$109.2K - $119.5K
3% of jobs
$119.5K - $129.8K
4% of jobs
$132.8K is the 25th percentile. Wages below this are outliers.
$129.8K - $140.1K
6% of jobs
The median wage is $146.6K / yr.
$140.1K - $150.5K
33% of jobs
$150.5K - $160.8K
3% of jobs
$160.8K - $171.1K
2% of jobs
$177.9K is the 75th percentile. Wages above this are outliers.
$171.1K - $181.4K
12% of jobs
$181.4K - $191.8K
5% of jobs
$191.8K - $202.1K
4% of jobs
$202.1K - $212.4K
12% of jobs
$98.8K
$157.9K
$212.4K
How much do internship asic rtl design engineer jobs pay per year?
As of Aug 12, 2026, the average yearly pay for internship asic rtl design engineer in Long Beach, CA is $157,927.00, according to ZipRecruiter salary data. Most workers in this role earn between $138,300.00 and $189,300.00 per year, depending on experience, location, and employer.
What does an internship ASIC RTL design engineer do?
As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.
What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?
To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.
What is an internship ASIC RTL design engineer?
An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.
What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?
| Aspect | Internship Asic Rtl Design Engineer | Asic Verification Engineer |
|---|---|---|
| Credentials | Typically pursuing or recently completed a degree in Electrical Engineering or Computer Engineering | Similar educational background, often with additional coursework in verification methodologies |
| Work Environment | Internship setting, supervised, focused on learning and assisting in RTL design tasks | Full-time role, focused on testing and verifying RTL designs |
| Industry Usage | Used in semiconductor and chip design companies during early career stages | Common in companies developing complex integrated circuits and chips |
The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Long Beach, CA? The most popular types of Asic Rtl Design Engineer jobs in Long Beach, CA are:
What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Long Beach, CA? For Internship Asic Rtl Design Engineer jobs in Long Beach, CA, the most frequently searched job titles are:
What job categories do people searching Internship Asic Rtl Design Engineer jobs in Long Beach, CA look for? The top searched job categories for Internship Asic Rtl Design Engineer jobs in Long Beach, CA are:
What cities near Long Beach, CA are hiring for Internship Asic Rtl Design Engineer jobs? Cities near Long Beach, CA with the most Internship Asic Rtl Design Engineer job openings:
$122K - $214K/yr
Full-time
Medical, Dental, Retirement
Re-posted 14 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification for PHY modem development.
Support banckend activities by reviewing the reports and appropriate adjustment of the design.
Involve in the pre and post silicon bringup process.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
Minimum Qualifications
Bachelors degree in related field.
Understanding of DSP fundamentals.
Digital Communications knowledge.
Proficiency in RTL Design.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $122,700 and $214,300, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification for PHY modem development.
Support banckend activities by reviewing the reports and appropriate adjustment of the design.
Involve in the pre and post silicon bringup process.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
Minimum Qualifications
Bachelors degree in related field.
Understanding of DSP fundamentals.
Digital Communications knowledge.
Proficiency in RTL Design.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $122,700 and $214,300, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976