ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
ASIC Engineer
New York, NY · On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
Hardware Engineer, RTL
New York, NY · On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...
Hardware Engineer, RTL
New York, NY · On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...
We expect interns to build hardware applications from concept to a working design; your projects ... both RTL design and testing/integration. If you'd like to learn more, you can read about our ...
We expect interns to build hardware applications from concept to a working design; your projects ... both RTL design and testing/integration. If you'd like to learn more, you can read about our ...
We expect interns to build hardware applications from concept to a working design; your projects ... both RTL design and testing/integration. If you'd like to learn more, you can read about our ...
We expect interns to build hardware applications from concept to a working design; your projects ... both RTL design and testing/integration. If you'd like to learn more, you can read about our ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
Hardware Engineer, FPGA
New York, NY · On-site
$200K - $400K/yr
As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...
Hardware Engineer, FPGA
New York, NY · On-site
$200K - $400K/yr
As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...
Senior Engineer, Physical Design Engineering (ASIC)
Somerset, NJ · On-site
$143K - $147K/yr
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Senior Engineer, Physical Design Engineering (ASIC)
Somerset, NJ · On-site
$143K - $147K/yr
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Previous internship experience in digital logic design * Expertise in networking protocols, CPU ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Previous internship experience in digital logic design * Expertise in networking protocols, CPU ...
Senior Engineer, Digital Design Engineering
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
Somerset, NJ · On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Senior Engineer, Digital Design Engineering
Somerset, NJ · On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Previous internship experience in digital logic design * Expertise in networking protocols, CPU ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Previous internship experience in digital logic design * Expertise in networking protocols, CPU ...
The FPGA/ASIC Design team and Verification team work in close collaboration, pushing boundaries in ... The Hardware Engineering Summer 2027 Internship offers candidates the opportunity to explore both ...
The FPGA/ASIC Design team and Verification team work in close collaboration, pushing boundaries in ... The Hardware Engineering Summer 2027 Internship offers candidates the opportunity to explore both ...
Hardware Engineer, Physical Design
New York, NY · On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro ...
Hardware Engineer, Physical Design
New York, NY · On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro ...
ASIC Technical Project Manager
New York, NY · On-site
$150K - $250K/yr
... engineering teams and external vendors to deliver high performance silicon on schedule. You will ... Coordinate handoffs and sign-off gates across architecture, RTL, DV, physical design ...
ASIC Technical Project Manager
New York, NY · On-site
$150K - $250K/yr
... engineering teams and external vendors to deliver high performance silicon on schedule. You will ... Coordinate handoffs and sign-off gates across architecture, RTL, DV, physical design ...
Electronics Design Engineer
$63K - $84K/yr
... programmable device digital RTL design, design debug and characterization, and design documentation for transfer to manufacturing and user support. Success will rely heavily on efficient ...
Electronics Design Engineer
$63K - $84K/yr
... programmable device digital RTL design, design debug and characterization, and design documentation for transfer to manufacturing and user support. Success will rely heavily on efficient ...
Internship Asic Rtl Design Engineer information
See Freehold, NJ salary details
$94.1K - $104K
16% of jobs
$104K - $113.8K
3% of jobs
$113.8K - $123.6K
4% of jobs
$126.5K is the 25th percentile. Wages below this are outliers.
$123.6K - $133.5K
6% of jobs
The median wage is $139.7K / yr.
$133.5K - $143.3K
33% of jobs
$143.3K - $153.1K
3% of jobs
$153.1K - $163K
2% of jobs
$169.5K is the 75th percentile. Wages above this are outliers.
$163K - $172.8K
12% of jobs
$172.8K - $182.6K
5% of jobs
$182.6K - $192.5K
4% of jobs
$192.5K - $202.3K
12% of jobs
$94.1K
$150.4K
$202.3K
How much do internship asic rtl design engineer jobs pay per year?
As of Sep 6, 2026, the average yearly pay for internship asic rtl design engineer in Freehold, NJ is $150,425.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,700.00 and $180,300.00 per year, depending on experience, location, and employer.
What is an internship ASIC RTL design engineer?
An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.
What does an internship ASIC RTL design engineer do?
As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.
What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?
To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.
What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?
| Aspect | Internship Asic Rtl Design Engineer | Asic Verification Engineer |
|---|---|---|
| Credentials | Typically pursuing or recently completed a degree in Electrical Engineering or Computer Engineering | Similar educational background, often with additional coursework in verification methodologies |
| Work Environment | Internship setting, supervised, focused on learning and assisting in RTL design tasks | Full-time role, focused on testing and verifying RTL designs |
| Industry Usage | Used in semiconductor and chip design companies during early career stages | Common in companies developing complex integrated circuits and chips |
The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.
What cities near Freehold, NJ are hiring for Internship Asic Rtl Design Engineer jobs?
Cities near Freehold, NJ with the most Internship Asic Rtl Design Engineer job openings:
Job description
About the Position
We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.
We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About You- Have 4+ years practical experience in RTL design and verification
- Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
- Front-end RTL design and synthesis
- Back-end physical design
- Verification (including formal)
- Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)
If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
About Jane Street
Sourced by ZipRecruiter
Industry
Finance and insurance
Company size
1,001 - 5,000 Employees
Headquarters location
New York, NY, US
Year founded
2000