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Internship Asic Rtl Design Engineer Jobs in Easley, SC

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

SNAP Diagnostics

Design Engineer 1

Anderson, SC · On-site

Design Engineer I - New Product Development Engineering (OPE) The Design Engineer I supports the ... Internship or co-op experience in product development or manufacturing. * Familiarity with ...

SNAP Diagnostics

Design Engineer II

Anderson, SC · On-site

Bachelor of Science in Mechanical Engineering or related engineering discipline. * 3-5 years of design experience in consumer, industrial, or electromechanical products (internship and co-op ...

MSI Mold Builders

Internship

Greenville, SC · On-site

Our customers rely on us to design and build various types of steel and aluminum molds for ... High School interns Exposed to all areas of MSI's production and engineering areas. The intern will ...

MSI Mold Builders

Internship

Greenville, SC

$15.75 - $20.50/hr

Our customers rely on us to design and build various types of steel and aluminum molds for ... Exposed to all areas of MSI's production and engineering areas. The intern will be assigned tasks ...

Garver

Project Engineer (Entry Level)

Greenville, SC · On-site

$63K - $83K/yr

The Project Engineer will be led by a Project Manager on a team consisting of multi-discipline ... internship experience related to design of water/wastewater systems * Master's degree in civil ...

Garver

Project Engineer (Entry Level)

Greenville, SC · On-site

$63K - $83K/yr

The Project Engineer will be led by a Project Manager on a team consisting of multi-discipline ... internship experience related to design of water/wastewater systems * Master's degree in civil ...

SNAP Diagnostics

Electrical Engineer Internship

Anderson, SC · On-site

$17.50 - $23/hr

As a TTI Electrical Engineering Intern, you would work with regular direction and guidance from a ... Design analysis and performing a wide variety of calculations and software aided analysis in the ...

CYNET SYSTEMS

Mechanical Engineer II

Greenville, SC · On-site

$44 - $49/hr

Coursework or internships supporting gas turbine design, repair, manufacturing, or services ... Mechanical Engineering. * Repair Non-Conformance Notifications (NCNs). * Built in Quality (BIQ)

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Easley, SC

Internship Asic Rtl Design Engineer information

See Easley, SC salary details

$88.2K

$140.9K

$189.5K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for internship asic rtl design engineer in Easley, SC is $140,937.00, according to ZipRecruiter salary data. Most workers in this role earn between $123,400.00 and $168,900.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Easley, SC?

For Internship Asic Rtl Design Engineer jobs in Easley, SC, the most frequently searched job titles are:

Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Easley, SC as of August 2026, with employment types broken down into 71% Full Time, and 29% Contract. Highlights an 74% In-person, and 26% Remote job distribution, with an average salary of $140,937 per year, or $67.8 per hour.

Senior FPGA Design Engineer

AERONIX INC

Greenville, SC • On-site

$145K - $175K/yr

Full-time

Posted 29 days ago

Job description


Job Title: Senior FPGA Engineer
Department: Engineering
Reports To: Functional Team Lead / Program Manager
FLSA Status: Exempt / Full-time

Salary Range: $145k - $175k Annually

DoD Secret clearance (or higher) REQUIRED.


ROLE

We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop the architecture, implementation, and verification of complex, high-speed FPGA solutions. The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

RESPONSIBILITIES

  • Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
  • Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
  • Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.
  • Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
  • Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
  • Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
  • Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

REQUIRED SKILLS

  • Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
  • Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
  • Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
  • Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
  • Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
  • Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).
  • Experience with System-on-Chip technologies.

PREFERRED SKILLS

  • Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
  • Familiarity with Universal Verification Methodology (UVM).
  • Familiarity with Microsemi Libero and Lattus Diamond.
  • Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.
  • Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.
  • Support JTAG Boundary scan design and testing
  • Experience with Cryptography, Digital Signal Processing and RF Applications
  • MATLAB modeling
  • Strong oral and written communication skills, with ability to document and present technical work clearly.
  • Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
  • Familiarity with Manufacturing processes, and Electronic Stress Screening.
  • Understanding of formal verification processes and compliance standards.

QUALIFICATIONS

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum 10 years of relevant experience in FPGA design.
  • Excellent written and verbal communication skills.
  • Ability to work in a collaborative team environment.
  • DoD Secret clearance (or higher) REQUIRED.
  • Position located in Melbourne, FL or Greenville, SC (not remote).