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Intern Soc Design Engineer Jobs in Edmonds, WA (NOW HIRING)

Actalent

Digital Design Engineer

Seattle, WA

$60 - $75/hr

Digital Design Engineer This role focuses on the end-to-end design and development of complex, multi-layer digital printed circuit boards (PCBs) for advanced processor, FPGA, and SoC-based systems.

Actalent

Digital Design Engineer

Seattle, WA · On-site

$60 - $75/hr

Digital Design Engineer This role focuses on the end-to-end design and development of complex, multi-layer digital printed circuit boards (PCBs) for advanced processor, FPGA, and SoC-based systems.

Actalent

Sr. Electrical Design Engineer III

Redmond, WA · Hybrid

$118K - $159K/yr

Electrical Design Engineer III - Digital High-Speed Design & Board Bring-Up This role focuses on ... Experience with processor-, FPGA-, and SoC-based hardware design and associated development ...

Actalent

Sr. Electrical Design Engineer III

Redmond, WA · Hybrid

$118K - $159K/yr

Electrical Design Engineer III - Digital High-Speed Design & Board Bring-Up This role focuses on ... Experience with processor-, FPGA-, and SoC-based hardware design and associated development ...

TEKsystems

Sr. Electrical Design Engineer III

Redmond, WA

$118K - $159K/yr

Description This is 2 electrical engineer contractor positions (digital and power focus) #1 Digital ... Experience with processor/FPGA/SoC-based hardware design and associated toolchains. * High-speed ...

Nvidia

Senior Digital Design Engineer

Redmond, WA · On-site

Collaborate with chip architects, verification engineers, formal verification engineers, and SoC ... Deep understanding of ASIC design flows and methodology * Strong analytical and interpersonal ...

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All JobsIntern Soc Design Engineer JobsIntern Soc Design Engineer Jobs in Edmonds, WA

Intern Soc Design Engineer information

See Edmonds, WA salary details

$10

$21

$40

How much do intern soc design engineer jobs pay per hour?

As of Aug 27, 2026, the average hourly pay for intern soc design engineer in Edmonds, WA is $21.28, according to ZipRecruiter salary data. Most workers in this role earn between $15.82 and $23.75 per hour, depending on experience, location, and employer.

What is the difference between Intern Soc Design Engineer vs Intern Hardware Design Engineer?

AspectIntern Soc Design EngineerIntern Hardware Design Engineer
Required SkillsDigital/analog circuit design, FPGA, PCB layout, scriptingCircuit schematic, PCB design, component selection, testing
Work EnvironmentSemiconductor companies, electronics firms, R&D labsConsumer electronics, industrial equipment, R&D teams
Common UsageFocus on system-on-chip (SoC) architecture and integrationFocus on hardware components and circuit implementation

Intern Soc Design Engineers typically work on integrated circuit architecture and system integration, while Intern Hardware Design Engineers focus on designing and testing physical hardware components. Both roles involve electronics fundamentals but differ in scope and specific technical skills.

What cities near Edmonds, WA are hiring for Intern Soc Design Engineer jobs?

Cities near Edmonds, WA with the most Intern Soc Design Engineer job openings:

Intern Soc Design Engineer jobs near you

Senior ASIC Physical Design Engineer

K2 Space

Seattle, WA

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 27 days ago

Job description

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
  • Develop and maintain scripts and automation to improve flow efficiency and consistency. 
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
  • Assist in chip-level integration, ECOs, and tapeout preparation. 
  • Contribute to methodology development, tool evaluation, and flow documentation. 
  • Support your product through production and spaceflight.  

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 
  • 5-10 years of experience in ASIC physical design for complex SoCs. 
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
  • Strong understanding of timing analysis, power optimization, and physical verification flows. 
  • Experience with hierarchical or flat SoC design methodologies. 
  • Familiarity with FinFET technologies. 
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs. 
  • Experience with chip-package co-design or advanced packaging (2.5D/3D). 
  • Familiarity with physical design service vendor management or offshore collaboration. 
  • Experience with sign-off through TSMC. 
  • Experience with Gate-All-Around technologies.  
  • Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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