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Intern Memory Design Engineer Jobs in Austin, TX

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in ... Because modern AI workloads push the limits of performance, memory, and efficiency, our RTL ...

ASIC Design Engineer

Austin, TX · On-site

$130 - $210/hr

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

Are you interested in joining Qualcomm's high performance CPU team as a Memory Designer? You will ... As a CPU SRAM Design Engineer, you will design, improve, and analyze digital circuits for memories.

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL ...

Senior RTL Design Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL ...

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the ... Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL ...

IC Package Design Engineer

Austin, TX · On-site

$134K/yr

... for a Package Design Engineer to drive the physical design and integration of advanced ... memory, RF, and cellular technologies. You will play a key role in shaping the architecture ...

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in memory compiler development is considered a plus, but not required. Experience ...

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Experience in memory compiler development is considered a plus, but not required. Experience ...

Digital Layout Design Engineer

Austin, TX · On-site

$140 - $200/hr

As part of ourDigital Design Engineering group, you'll take imaginative and revolutionaryideas and ... Experience in memory compiler development is considered a plus, but notrequired. Experience ...

... for a Package Design Engineer to drive the physical design and integration of advanced ... memory, RF, and cellular technologies. You will play a key role in shaping the architecture ...

... for a Package Design Engineer to drive the physical design and integration of advanced ... memory, RF, and cellular technologies. You will play a key role in shaping the architecture ...

... for a Package Design Engineer to drive the physical design and integration of advanced ... memory, RF, and cellular technologies. You will play a key role in shaping the architecture ...

Showing results 21-40

Intern Memory Design Engineer information

See Austin, TX salary details

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$19

$36

How much do intern memory design engineer jobs pay per hour?

As of Aug 18, 2026, the average hourly pay for intern memory design engineer in Austin, TX is $19.21, according to ZipRecruiter salary data. Most workers in this role earn between $14.28 and $21.44 per hour, depending on experience, location, and employer.

What does an intern memory design engineer do?

An Intern Memory Design Engineer assists in the design, development, and testing of computer memory components such as DRAM, SRAM, or Flash memory. They work closely with senior engineers to create circuit schematics, run simulations, analyze data, and help optimize memory performance. Interns may also participate in debugging and validation of memory products, learning industry-standard design tools and methodologies. This role provides valuable hands-on experience in semiconductor design and the opportunity to contribute to real-world projects.

What are the key skills and qualifications needed to thrive as an intern memory design engineer, and why are they important?

To thrive as an Intern Memory Design Engineer, you need a solid background in electrical engineering, digital/analog circuit design, and semiconductor fundamentals, often supported by ongoing or completed coursework toward a relevant degree. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and basic knowledge of scripting languages like Python or TCL, are typically required. Strong analytical thinking, attention to detail, and effective communication set standout interns apart in collaborative engineering environments. These skills and qualities are crucial for designing reliable memory components and contributing efficiently to complex, team-driven projects.

What are some common challenges faced by an intern memory design engineer during their internship?

As an Intern Memory Design Engineer, you may encounter challenges such as understanding complex circuit design concepts and adapting to industry-standard Electronic Design Automation (EDA) tools. Working in this role often involves collaborating closely with experienced engineers and cross-functional teams to verify and optimize memory layouts for performance and reliability. Navigating the steep learning curve and balancing hands-on project work with ongoing training can be demanding, but these experiences are invaluable for building foundational skills and industry knowledge.

What are the most commonly searched types of Memory Design Engineer jobs in Austin, TX?

The most popular types of Memory Design Engineer jobs in Austin, TX are:

What job categories do people searching Intern Memory Design Engineer jobs in Austin, TX look for?

The top searched job categories for Intern Memory Design Engineer jobs in Austin, TX are:

What cities near Austin, TX are hiring for Intern Memory Design Engineer jobs?

Cities near Austin, TX with the most Intern Memory Design Engineer job openings:

Infographic showing various Intern Memory Design Engineer job openings in Austin, TX as of July 2026, with employment types broken down into 87% Full Time, 10% Part Time, and 3% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $39,950 per year, or $19.2 per hour.

$120K - $225K/yr

Full-time

Re-posted 26 days ago


Job description

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
 
About Us:
Mythic is building the future of AI computing with breakthrough analog technology that delivers 100 the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 C to +125 C, making it ideal for industrial, automotive, aerospace, and defense.
 
We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
 
The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location.
 
RTL Design at Mythic:
At Mythic, our RTL design team is at the heart of transforming our custom dataflow architecture into working silicon. RTL engineers take ownership of microarchitecture and RTL implementation, designing high-performance, low-power logic that enables our breakthrough AI hardware. The team works closely with architecture, custom analog IP, compiler, verification, emulation, and post-silicon teams to ensure every component integrates seamlessly into the full system. Because modern AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness. We welcome engineers at all levels who are excited to tackle challenging design problems and play a key role in building the next generation of AI compute hardware.
Responsibilities
  • Design and implement RTL for Mythic's next-generation AI processor.
  • Develop and optimize high-performance, low-power components including datapaths, controllers, memory subsystems, and interconnects.
  • Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness.
  • Drive timing closure by working with synthesis and physical design teams.
  • Participate in design reviews and contribute to improving RTL coding practices and methodologies.
Requirements
  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 3+ years of industry experience in RTL design, microarchitecture, and architecture development.
  • Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).
  • Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
  • Familiarity with timing constraints, physical design considerations, and EDA flows.
  • Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.
  • Strong problem-solving and communication skills with ability to work in cross-functional teams.
At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.
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