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Intern Circuit Design Engineer Jobs in California

Intel

Analog Circuit Design Engineer

Santa Clara, CA · On-site

$122K - $232K/yr

  • Medical

  • Retirement

  • PTO

As an Analog Circuit Design Engineer, you will play a pivotal role in designing, developing, and optimizing cutting-edge analog and mixed-signal circuits that power Intel's advanced process nodes.

Nvidia

Senior Circuit Design Engineer

Santa Clara, CA · Hybrid

$122K - $164K/yr

We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in improving the netlist and timing ...

Apple

SerDes Circuit Design Engineer

San Diego, CA · On-site

... junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO ... digital design concepts Experience and solid understanding of Tx/Rx equalization techniques and ...

Apple

SerDes Circuit Design Engineer

Cupertino, CA · On-site

... junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO ... digital design concepts Experience and solid understanding of Tx/Rx equalization techniques and ...

Apple

SerDes Circuit Design Engineer

Cupertino, CA · On-site

... junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO ... digital design concepts Experience and solid understanding of Tx/Rx equalization techniques and ...

Apple

SerDes Circuit Design Engineer

Cupertino, CA

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

... junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO ... digital design concepts Experience and solid understanding of Tx/Rx equalization techniques and ...

Apple

SerDes Circuit Design Engineer

San Diego, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

... junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO ... digital design concepts Experience and solid understanding of Tx/Rx equalization techniques and ...

Altera

Senior FPGA Circuit Design Engineer

San Jose, CA · On-site

$149K - $215K/yr

Provide technical guidance and mentorship to less-experienced engineers and serve as a technical resource for complex FPGA circuit and IP design challenges. * Support silicon bring-up and post ...

New

Apple

SerDes Circuit Design Engineer

Cupertino, CA

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

... junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO ... digital design concepts Experience and solid understanding of Tx/Rx equalization techniques and ...

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Analog Circuit Design Engineer

Intel

Santa Clara, CA • On-site

$122K - $232K/yr

Full-time

Medical, Retirement, PTO

Re-posted 28 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 159 rated electronics manufacturers

Job description

Job Details:Job Description: 
About Intel:
At Intel, we strive to create innovative technologies that shape the future of computing and empower every person and organization on the planet. This position offers a unique opportunity to innovate and impact Intel's Data Center and AI product lines, ensuring high-quality and efficient designs that drive meaningful change in the technology landscape.
Position Overview:
As an Analog Circuit Design Engineer, you will play a pivotal role in designing, developing, and optimizing cutting-edge analog and mixed-signal circuits that power Intel's advanced process nodes. You will collaborate with cross-disciplinary teams to bring high-performance, low-power solutions to life, contributing to Intel's success in delivering world-class products.
Key Responsibilities:
  • Design and develop complex analog and mixed-signal circuits, including transmitters (TX), receivers (RX), amplifiers, filters, clocking systems, and on-die voltage regulators
  • Perform circuit analysis and tradeoffs to optimize power, performance, area, timing, and yield
  • Create and validate behavioral models for analog and mixed-signal IPs for system-level integration
  • Develop and oversee floorplans and layouts while ensuring adherence to design rules and robustness
  • Conduct small signal analysis, stability testing, and compensation of feedback loops to meet performance specifications
  • Collaborate with architecture, layout, and validation teams to ensure seamless integration of designs into products
  • Author microarchitecture specifications, test plans, and documentation for design verification and validation
  • Conduct post-silicon validation and debug to ensure design functionality and performance meet product requirements
  • Provide technical mentorship and contribute to design reviews to enhance team-wide engineering excellence
  • Leverage industry-standard tools and methodologies, such as Synopsys and Cadence, for design and simulation
You should demonstrate the following professional traits to be successful:
  • Effective collaborator who works well across cross-disciplinary teams including architecture, layout, and validation
  • Strong problem-solver with a system-level mindset and the ability to navigate complex technical tradeoffs
  • Committed to engineering excellence through mentorship, thorough documentation, and active participation in design reviews
Qualifications:

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering or Computer Engineering with 3+ years of experience, or Master's degree in Electrical Engineering or Computer Engineering with 2+ years of experience, or a PhD in Electrical Engineering or Computer Engineering
The years of experience must include the following:
  • VLSI analog circuit design, small-signal analysis, and understanding of foundational digital design concepts
  • Synopsys and Cadence design tools and flows
  • Design optimization techniques related to performance, power, and area

Preferred Qualifications

  • Knowledge of high-speed IO signaling, transmission line theory, and power delivery concepts
  • Familiarity with PLLs, ADCs, DACs, switched-capacitor circuits, and noise analysis methodologies
  • Experience with scripting, Matlab, and post-silicon characterization using lab tools such as oscilloscopes and signal generators
  • Cross-disciplinary knowledge in analog integration, RTL, static timing analysis, and power grid design
  • Proven track record of system-level understanding, problem-solving, and effective collaboration in a team setting
  • VS Code, Python, and GitHub Copilot
Join us to innovate, lead, and create technologies that make a difference. Apply today and become part of a company that is shaping the future of technology and fostering a culture of innovation and collaboration.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Folsom, US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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