PRINCIPAL ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for ...
PRINCIPAL ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for ...
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Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
SR ASIC Design Verification Engineer
San Jose, CA · On-site
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
SR ASIC Design Verification Engineer
San Jose, CA · On-site
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Senior ASIC Design Verification Engineer (Technical role) Position Description: As a technical member of Micron's ASIC Design Verification team, you will have a key role in development of advanced ...
Sr. ASIC Design Verification Engineer
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
Sr. ASIC Design Verification Engineer
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
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Sr. ASIC Design Verification Engineer
San Jose, CA · On-site
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
Sr. ASIC Design Verification Engineer
San Jose, CA · On-site
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
ASIC Design Verification Engineer
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to-end verification of design blocks and top-level * Develop simulation models, test plans, direct and ...
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$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to-end verification of design blocks and top-level * Develop simulation models, test plans, direct and ...
Role Overview As a zeroRISC SoC/ASIC Design Verification Engineer, you will develop, verify, and maintain silicon in security-sensitive settings, including root-of-trust technology. You will elevate ...
Quick apply
Role Overview As a zeroRISC SoC/ASIC Design Verification Engineer, you will develop, verify, and maintain silicon in security-sensitive settings, including root-of-trust technology. You will elevate ...
ASIC Design Verification Engineer
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to-end verification of design blocks and top-level * Develop simulation models, test plans, direct and ...
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$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Perform end-to-end verification of design blocks and top-level * Develop simulation models, test plans, direct and ...
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ASIC Design Verification Engineering Technical Leader
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Participate in the ASIC design verification for Cisco high-end switching products. * Lead, architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment ...
SR ASIC Design Verification Engineer
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
SR ASIC Design Verification Engineer
$165K - $241.40K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
ASIC design/verification engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
ASIC Design Verification Engineering Technical Leader
San Jose, CA · On-site
$183.80K - $263.60K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Lead, architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment ...
ASIC Design Verification Engineering Technical Leader
San Jose, CA · On-site
$183.80K - $263.60K/yr
Participate in the ASIC design verification for Cisco high-end switching products. * Lead, architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment ...
Intern Asic Design Verification information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do intern asic design verification jobs pay per hour?
$210K - $295K/yr
Other
Medical, Dental, Vision, Life, Retirement, PTO
Posted 23 days ago
SpaceX rating
8.7
Based on 142 frontline employees who took The Breakroom Quiz
12th of 59 rated aerospace companies
Job description
PRINCIPAL ASIC DESIGN VERIFICATION ENGINEER (STARSHIELD)
Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Verification Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.
RESPONSIBILITIES:
- Responsible for digital ASIC verification at block and system level
- Lead and execute verification test plan, development, and milestones from beginning to end, develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
- Responsible for test plan execution, running regressions, code and functional coverage closure
- Automate test case generation by using Python and MATLAB programs
- Contribute to pre-silicon verification, chip bring-up and post-silicon validation
- Be a hands-on self-starter who can execute the steps required to fully verify complex digital designs
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering, or computer science
- 10+ years of experience with design verification and test bench development
PREFERRED SKILLS AND EXPERIENCE:
- Advanced degree in electrical engineering or computer engineering
- Experience with verification methodologies such as UVM/OVM/VMM
- Strong object-oriented programming knowledge
- Strong problem-solving and coding skills
- Experience in constrained random verification
- Expertise in developing test plans, implementing coverage models, and analyzing results
- Experience with scripting languages, e.g. Python for automation
- RTL design, chip bring-up, and post-silicon validation experience
- Ability to work in a dynamic environment with changing needs and requirements
- Ability to work in a dynamic environment with changing needs and requirements
- Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
- Enjoy being challenged and learning new skills
ADDITIONAL REQUIREMENTS:
- Ability to work long hours and weekends as necessary to support critical milestones
- Willingness to travel for off-site testing
- An active clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing
COMPENSATION AND BENEFITS:
Pay range:
Principal ASIC Design Verification Engineer: $210,000.00 - $295,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $20,000 annually, once officially briefed into a classified program.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
About SpaceX
Sourced by ZipRecruiter
Industry
Accounting services
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US
Year founded
2002