Proficiency in Verilog, build and verification tools (VCS or equivalent simulation tools, debug ... Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform ...
Proficiency in Verilog, build and verification tools (VCS or equivalent simulation tools, debug ... Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform ...
Proficiency in Verilog, build and verification tools (VCS or equivalent simulation tools, debug ... Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform ...
Proficiency in Verilog, build and verification tools (VCS or equivalent simulation tools, debug ... Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist ... Verification(DRC, LVS) and Power Analysis(IR drop, EMIG) on 45nm, 22nm, 14nm, or lower process ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist ... Verification(DRC, LVS) and Power Analysis(IR drop, EMIG) on 45nm, 22nm, 14nm, or lower process ...
Senior SoC Physical Design & Verification Engineer
Beaverton, OR · On-site
$130 - $160/hr
Knowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full-chip flows * Scripting skills perl/python/tcl to debug flow related issues ...
Senior SoC Physical Design & Verification Engineer
Beaverton, OR · On-site
$130 - $160/hr
Knowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full-chip flows * Scripting skills perl/python/tcl to debug flow related issues ...
Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. Strong communication and interpersonal skills are required along ...
Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. Strong communication and interpersonal skills are required along ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Verilog expertise is preferredas is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. * Strong communication and interpersonal skills are required along ...
Verilog expertise is preferredas is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO. * Strong communication and interpersonal skills are required along ...
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab ...
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab ...
Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab ...
Working closely with architecture, design, and software teams, you will help drive verification ... ASIC designs. 3+ years of experience in UVM and constrained random verification methods. 2+ years ...
New
Working closely with architecture, design, and software teams, you will help drive verification ... ASIC designs. 3+ years of experience in UVM and constrained random verification methods. 2+ years ...
New
Senior Design Verification Engineer - Neuromorphic Computing
Hillsboro, OR · On-site
$122 - $232/hr
Working closely with architecture, design, and software teams, you will help drive verification ... ASIC designs. * 3+ years of experience in UVM and constrained random verification methods. * 2+ ...
Posted today
Senior Design Verification Engineer - Neuromorphic Computing
Hillsboro, OR · On-site
$122 - $232/hr
Working closely with architecture, design, and software teams, you will help drive verification ... ASIC designs. * 3+ years of experience in UVM and constrained random verification methods. * 2+ ...
Posted today
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
This role supports architecture, design, implementation, verification, and lab validation in a ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
This role supports architecture, design, implementation, verification, and lab validation in a ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
This role supports architecture, design, implementation, verification, and lab validation in a ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$154K - $247K/yr
This role supports architecture, design, implementation, verification, and lab validation in a ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$155 - $248/hr
This role supports architecture, design, implementation, verification, and lab validation in a ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
Semiconductor Design Engineer (Compute Test, Oregon)
Tualatin, OR · On-site
$155 - $248/hr
This role supports architecture, design, implementation, verification, and lab validation in a ... Experience with Xilinx and/or Intel FPGAs; standard cell ASIC design experience preferred.
What we need to see: BS / MS or equivalent experience. 6+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown ...
What we need to see: BS / MS or equivalent experience. 6+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown ...
What we need to see: * BS / MS or equivalent experience. * 6+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown ...
What we need to see: * BS / MS or equivalent experience. * 6+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown ...
Director, SoC Design Engineering
$148K - $180K/yr
In this strategic role, you will define and implement scalable and reusable verification ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Director, SoC Design Engineering
$148K - $180K/yr
In this strategic role, you will define and implement scalable and reusable verification ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Intern Asic Design Verification information
See Portland, OR salary details
$9.69 - $12.35
9% of jobs
$12.35 - $15.02
8% of jobs
$15.71 is the 25th percentile. Wages below this are outliers.
$15.02 - $17.68
28% of jobs
The median wage is $18.39 / hr.
$17.68 - $20.35
16% of jobs
$22.17 is the 75th percentile. Wages above this are outliers.
$20.35 - $23.01
20% of jobs
$23.01 - $25.68
9% of jobs
$25.68 - $28.34
4% of jobs
$28.34 - $31.01
1% of jobs
$31.01 - $33.67
1% of jobs
$33.67 - $36.34
1% of jobs
$36.34 - $39
2% of jobs
$9
$20
$39
How much do intern asic design verification jobs pay per hour?
As of Sep 4, 2026, the average hourly pay for intern asic design verification in Portland, OR is $20.55, according to ZipRecruiter salary data. Most workers in this role earn between $15.29 and $22.93 per hour, depending on experience, location, and employer.
What cities near Portland, OR are hiring for Intern Asic Design Verification jobs?
Cities near Portland, OR with the most Intern Asic Design Verification job openings:
Key responsibilities
Develop and implement a high-performance MMU for GPUs, contributing to architecture decisions.
Collaborate with architects, designers, and software engineers across sites to accomplish development goals.
Mentor other engineers on the team and contribute to the development and micro-architecture of the MMU.
Nvidia rating
9.6
Based on 18 frontline employees who took The Breakroom Quiz
6th of 247 rated software companies
Job description
We are now looking for a Senior ASIC Engineer. NVIDIA is searching for an outstanding ASIC Engineer to build and implement an MMU for the world's top SoCs and GPUs. This position provides an opportunity to influence a dynamic technology company's products, from consumer graphics to autonomous vehicles.
Positioned at the leading edge of artificial intelligence and deep learning, NVIDIA drives innovation in modern computing. Our team of remarkable professionals works worldwide, aiming to push the boundaries of today's possibilities and shape the future computing platform. As a member of the MMU team, you will contribute to the development and implementation of a state-of-the-art memory management system with complex build requirements.
Our approach delivers the performance required by autonomous vehicles, photo-realistic games and applications, as well as the world's leading supercomputers. What you'll be doing: As a Senior Design Engineer at NVIDIA, you will be responsible for the development and micro-architecture of a high-performance MMU for a GPU using advanced verification methodologies. Contribute to architecture decisions.
Mentor other engineers on the team. Collaborate with architects, designers, and software engineers across sites to accomplish your goals. What we need to see: Bachelors or Masters Degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience.
5+ years of relevant work or research experience. Experience crafting memory subsystem units with properties such as memory coherency and arbitration policies. Proficiency in Verilog, build and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, Synopsys).
A solid understanding of Object-Oriented Programming with C++ and/or SystemVerilog. Strong communication skills are required. NVIDIA is widely considered to be one of the technology world's most desirable employers.
We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous. Do you love the challenge of crafting the highest performance & lowest power silicon possible.
If so, we want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until July 26, 2026.
This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.
As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US