Intel Wafer Level Assembly Jobs (NOW HIRING)

Overview of Role

We are seeking an enthusiastic and highly experienced professional in advanced semiconductor packaging technology to join our Field Technical Solutions team. This pivotal role involves dynamic collaboration with leading customers, our North American sales force, and our global engineering headquarters. Our mission is to empower customers to rapidly and efficiently design their next generation of 'must-have' products. This is achieved by deeply understanding their technical needs, then defining, promoting, and enabling the most competitive and innovative packaging solutions within our cutting-edge 3DFabric technology portfolio. You will report to the Director of the Field Technical Solutions-Advanced Packaging Department. Currently, we are operating in a hybrid work schedule with four days in the office.

Responsibilities

• Build relationships and trust with customers through technical interaction.
• Own the technical solution for customers and champion their needs.
• Justify the packaging business by understanding customers' products, roadmaps, and technical needs in advanced packaging technologies.
• Identify and drive internals teams to develop competitive and creative technical solutions.
• Host the engagement meetings between customer and internal teams on engineering/technology discussions.
• Provide local technical support together with sales team to customers as required.
• Introduce/train customers on our 3DFabric technology to enable them to create world class products.
• Ensure clear and accurate external and internal communication.
• Be a technical expert in NA office in advanced packaging, supporting customer engagement and internal technology alignment.
• Manage customer projects for advanced 2.5D/3D packaging, including those for leading AI/HPC applications, guiding them from conceptualization through production qualification.
• Communicate with customers on package architecture and floor planning based on design rules and simulation/modeling (themo-mechanical and thermal simulation) outcomes for feasibility evaluation and floor plan optimization.
• Direct substrate technology development, collaborating with external suppliers and internal teams to explore advanced materials (e.g., low Dk/Df ABF, low CTE) and multi-layer core schemes.
• Conduct comprehensive research and competitive analysis of advanced 2D/3D packaging technologies across the global semiconductor industry to influence strategic direction.
• Lead and coordinate cross-functional review meetings involving various stakeholders (e.g., design, quality, process development/integration, testing, product teams) for complex project development.
• Coordinate HQ resources on failure analysis and root cause finding during package development phase in order to deliver customer products.

Minimum Qualifications

• Master's Degree, or above, in Mechanical Engineering, Materials Science/Engineering, Electrical Engineering, or Electro-Optical Engineering.
• Proven, strong technical background with 12+ years of industry experience in advanced semiconductor packaging.
• Extensive hands-on experience with cutting-edge advanced packaging technologies, such as:
• 2.5D/3D Packaging (e.g., CoWoS, InFO, SoIC, or similar advanced wafer-level integration schemes).
• Bonding Technologies (e.g., Wafer-on-Wafer bonding, Chip-on-Wafer bonding) and assembly technologies (e.g. flip chip, reflow, TCB, etc.)
• Heterogeneous Integration (e.g., 3DIC and other advanced heterogeneous packages) from concept/architecture to execution.
• Specific areas of expertise such as photonic packaging (Si-Photonic integration, Co-Packaged Optics - CPO), thermal/thermos-mechanical simulation/modeling are highly valued.
• Demonstrated expertise in packaging process development, Wafer-Level System Integration, and manufacturing capabilities expansion.
• Profound knowledge of chip-package interaction, assembly processes, thermo-mechanical behavior of packages and their materials, and electrical performance requirements on packages.
• Understanding of packaging design flow and concepts (including EDA tools), electrical functional tests, and reliability/qualification tests.

Preferred Qualifications

• Ph.D. in Materials Science and Engineering, Mechanical Engineering, Electrical Engineering, or Electro-Optical Engineering.
• Experience with advanced packaging process development and production, chip-package interaction, board-level reliability, and package qualification.
• Proven ability to lead cross-functional teams and manage complex technical projects from concept to production.
• Familiarity with substrate/PCB board technology development, design rules, and advanced material selection.
• Experience with Failure Analysis (FA) and root cause finding for advanced packaging, thermo-mechanical/mechanical simulation/modeling, or thermal simulation/modeling.
• Good communication skills and experienced in program/project management.
• Self-motivated with a desire to learn and engage.
• A portfolio of patents or significant intellectual property contributions in advanced packaging is a strong plus.

About Our Company

Join a global leader at the forefront of semiconductor innovation. As the world's premier dedicated semiconductor foundry, TSMC pioneered the pure-play business model in 1987 and continue to set the industry standard for manufacturing excellence and technological advancement. We are driven by a commitment to innovation, pushing the boundaries of semiconductor manufacturing to enable the future of technology.

We empower a thriving ecosystem of global customers and partners with industry-leading process technologies and comprehensive design enablement solutions. With operations spanning Asia, Europe, and North America, we act as a committed corporate citizen worldwide.

In North America, our robust sales and service organization collaborates closely with customers, ensuring their silicon success through cutting-edge technologies and unparalleled manufacturing capabilities. We are accelerating our R&D investment, expanding our manufacturing footprint, and growing our talent base to support the next wave of customer innovation.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, our North America entity may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon our North America entity obtaining any export license or other approval that may be required by the U.S. Government.  

Diversity statement

TSMC North America is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.

TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at G_Accommodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC's obligations under applicable employment law. Reasonable accommodations will be arranged on a case-by-case basis. 

Pay Transparency

At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $125,000 and $210,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC's total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.