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Intel Product Owner Jobs (NOW HIRING)

Intel

Senior Density Fill Development Engineer

Austin, TX · On-site

$103K - $142K/yr

... Intel's hardware product design and manufacturing processes. Your work will enable design teams to ... Collaborate with process developers, design rule owners, and end users to define requirements and ...

Intel

Senior Density Fill Development Engineer

Hillsboro, OR · On-site

$113K - $156K/yr

... Intel's hardware product design and manufacturing processes. Your work will enable design teams to ... Collaborate with process developers, design rule owners, and end users to define requirements and ...

Intel

Senior Density Fill Development Engineer

Phoenix, AZ · On-site

$103K - $142K/yr

... Intel's hardware product design and manufacturing processes. Your work will enable design teams to ... Collaborate with process developers, design rule owners, and end users to define requirements and ...

BAE Systems

Business Intel Anst I

Nashua, NH · On-site

$52 - $69.50/hr

Work closely with the Product Owner and Manager to keep the backlog refined, prioritized, and ready for development. * Ensure every story and task has clear acceptance criteria and a documented ...

RPMGlobal

Sell Through Manager

Irvine, CA · On-site

... intel. Maintain ongoing review and tracking of product category sell‑out data, turnover and ... Supports Sr. Sell Through Manager, Product Owners. May have functional support from Sell Through ...

Parsons

$148K - $266K/yr

Acting as the Product Owner Analyst (POA) for the Systems Engineering Team, collaborating within ... Hands-on experience with military/intel data standards (e.g., Cursor on Target (CoT), FMV & KLV ...

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Intel Product Owner information

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How much do intel product owner jobs pay per year?

As of Sep 13, 2026, the average yearly pay for intel product owner in the United States is $112,891.00, according to ZipRecruiter salary data. Most workers in this role earn between $93,500.00 and $129,500.00 per year, depending on experience, location, and employer.

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Senior Density Fill Development Engineer

Hillsboro, OR • On-site

Intel Corporation
Manufacturing • 10K+ employees
Learn more about Intel Corporationexternal

Full-time

Medical, Retirement, PTO

Posted 27 days ago

Key responsibilities

  • Design, develop, and debug Fill components of Process Design Kits (PDKs).

  • Provide algorithmic solutions to address density deficiencies and ensure manufacturability compliance.

  • Automate workflows to enhance efficiency, accuracy, and deployment across design teams.

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

Job description

Job Details:
Job Description:
The Role and Impact
Join Intel's Design Technology Platform (DTP) organization and become an integral part of a highly skilled team driving the development of cutting-edge technologies. As an EDA Tools Software Engineer, you will design, develop, test, and debug software tools and methodologies that directly support Intel's hardware product design and manufacturing processes. Your work will enable design teams to innovate faster, meet complex manufacturability constraints, and deliver industry-leading products to market. By contributing to Intel's advanced process technologies, you will play a pivotal role in achieving leadership in design automation and fostering a culture of innovation.
Key Responsibilities
  • Design, develop, and debug Fill components of Process Design Kits (PDKs),
  • Provide algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance.
  • Collaborate with process developers, design rule owners, and end users to define requirements and implement state-of-the-art solutions.
  • Automate workflows to enhance efficiency, accuracy, and deployment across design teams.
  • Develop comprehensive test cases and systems to validate software tools and ensure seamless integration with various design methodologies.
  • Innovate and drive advancements in EDA tools and methodologies to meet the evolving needs of Intel's technology ecosystem.
  • Partner with cross-functional teams and external EDA vendors to define and implement new tool features and methodologies.
  • Maintain documentation, including training materials and user guides, to support customers and ensure robust deployment.

In this role, you will have a unique opportunity to make a lasting impact by enabling Intel's success in the competitive semiconductor landscape. Take the next step in your career and join a team where your expertise will help shape the future of technology innovation.
Qualifications:
Minimum Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience, Master's degree with 5+ years of experience, or PhD with 2+ years of experience.
  • Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment.
  • 3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications.
  • Solid understanding of semiconductor device physics, process technology, and design rules.
  • Experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes.
  • Strong knowledge of Unix/Linux platforms and computing environments.

Preferred Qualifications
  • 5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization.
  • Experience with advanced physical verification techniques, including DRC, and density/fill modules.
  • Industry experience with other foundry technologies in this domain is strongly desirable
  • Familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer.
  • Deep understanding of technology scaling challenges and their impact on physical design rules.
  • Proven track record of collaborating across multiple internal and external teams to deliver optimal solutions.
  • Exceptional analytical and problem-solving skills with the ability to address cross-disciplinary challenges.
  • Strong written and verbal communication skills, with the ability to present complex technical concepts clearly.
  • Leadership experience driving innovation, process improvements, or cross-functional initiatives.
  • Strong preference for candidates with experience from semiconductor foundries, advanced packaging organizations (OSATs), integrated device manufacturers (IDMs), or EDA vendors, where they have contributed to physical verification, density-fill methodology development, process design kits (PDKs), or manufacturing-driven design solutions.

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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