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Intel Packaging Engineer Jobs (NOW HIRING)

Cspeed

FEA Packaging Engineer

Palo Alto, CA · On-site

... Tesla, Apple, Samsung, Intel, and VMware. Cspeed IO is developing next-generation optical ... packages across both thermal and structural domains. It is scoped for a strong FEA engineer ...

Intel

$18.25 - $23.75/hr

Silicon & Packaging Engineer * Emerging Technologies & Research roles Build technical expertise ... Intel sponsors individuals for employment-based visas for positions where we experience a shortage ...

Intel

$18 - $23.25/hr

Silicon & Packaging Engineer * Emerging Technologies & Research roles Build technical expertise ... Intel sponsors individuals for employment-based visas for positions where we experience a shortage ...

Intel

$16.50 - $21.50/hr

Silicon & Packaging Engineer * Emerging Technologies & Research roles Build technical expertise ... Intel sponsors individuals for employment-based visas for positions where we experience a shortage ...

Intel

$18 - $23.25/hr

Silicon & Packaging Engineer * Emerging Technologies & Research roles Build technical expertise ... Intel sponsors individuals for employment-based visas for positions where we experience a shortage ...

Intel

$19.75 - $25.50/hr

Silicon & Packaging Engineer * Emerging Technologies & Research roles Build technical expertise ... Intel sponsors individuals for employment-based visas for positions where we experience a shortage ...

Intel

$19.75 - $25.50/hr

Silicon & Packaging Engineer * Emerging Technologies & Research roles Build technical expertise ... Intel sponsors individuals for employment-based visas for positions where we experience a shortage ...

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As of Sep 9, 2026, the average hourly pay for intel packaging engineer in the United States is $42.37, according to ZipRecruiter salary data. Most workers in this role earn between $32.69 and $49.28 per hour, depending on experience, location, and employer.

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Infographic showing various Intel Packaging Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $88,120 per year, or $42.4 per hour.

FEA Packaging Engineer

Palo Alto, CA • On-site

Cspeed
See more jobs at Cspeedexternal

Full-time

Re-posted 6 days ago

Job description

Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true "scale-up" architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
The Role
This position performs finite element analysis for CspeedIO optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in either thermal or mechanical analysis is expected, and the ability to work competently in the other is required.
The analysis supports package architecture decisions and qualification. Temperature governs optical wavelength and channel uniformity. Deformation and interconnect stress govern assembly yield, reliability, and optical coupling, since warpage displaces optical facets. Both sets of results terminate in the same design decisions, which is why the scope is held in one role.
Correlation against measured hardware is a standing expectation. Results are used for design sign-off, so assumptions must be documented and defensible.
Responsibilities
Thermal analysis
  • Build and maintain thermal models spanning die, package, interface materials, lid, and cold plate, and establish cooling boundary conditions and their validity limits.
  • Resolve the temperature field across the photonic IC to the resolution photonic design requires, and define the heat extraction path and interface material selection for high-flux die within the assembly.

Structural analysis
  • Predict warpage through the assembly process, and own the flatness, coplanarity, and facet planarity budgets that assembly and optical coupling depend on.
  • Analyze bump and interconnect stress, chip-package interaction, and fatigue life, supporting qualification against JEDEC or equivalent methodology.

Methodology and correlation
  • Define modeling standards and document assumptions such that results are auditable.
  • Lead correlation against measured temperature, warpage, cross-section, and reliability data, and revise methodology accordingly.

Design and supplier support
  • Provide requirements, constraints, and sign-off criteria during architecture definition rather than after design freeze.
  • Engage substrate suppliers, OSATs, and cooling and material vendors on process assumptions and measured data.
Required Qualifications
  • MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
  • 6+ years of finite element analysis for semiconductor packaging or electronic systems, including one product carried from architecture through hardware correlation.
  • Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain - for example Ansys Mechanical or Abaqus alongside Icepak, Fluent, Flotherm, or Celsius.
  • Sound FEA fundamentals: meshing judgment, boundary condition selection, convergence, and the ability to defend a model rather than only to run one.
  • Demonstrated correlation of simulation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.
  • Experience with advanced packaging construction: flip chip, 2.5D/3D, interposers, and heterogeneous integration.
Preferred Qualifications
  • Depth in nonlinear and time-dependent material behavior: creep, viscoplasticity, viscoelasticity, and fatigue.
  • Silicon photonics or optoelectronic packaging, including thermo-optic sensitivity or warpage as an optical alignment constraint.
  • Coupled thermal-structural workflows, including transfer of a computed temperature field into a structural model.
  • Direct-to-chip liquid cooling, or chip-package interaction and low-k dielectric stress.
  • Scripting for model automation and parametric studies, and design of experiments methodology.
Scope and Impact
This position provides the physics basis for package architecture decisions and qualification.

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