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Ic Test Manager Jobs (NOW HIRING)

Altera

Product Development Engineer

San Jose, CA · On-site

$106K - $153K/yr

... Device Manager (SDM), configuration interfaces, reset controllers, boot flows, and related ... Experience in IC design and IC test. * Experience with FPGA Reset, Configuration, SDM, or DFX ...

Altera

Product Development Engineer

San Jose, CA · On-site

$106K - $153K/yr

... Device Manager (SDM), configuration interfaces, reset controllers, boot flows, and related ... Experience in IC design and IC test.* Experience with FPGA Reset, Configuration, SDM, or DFX ...

Foxconn WI

IC Programmer

Mount Pleasant, WI · On-site

The IC Programmer will maintain equipment, manage inventory of programming materials, and coordinate timely delivery of programmed parts while assisting the Test Department as needed.

VT Group (VTG)

Test Systems Engineer

Springfield, VA · On-site

... Management Information Systems, or related STEM degree program, or related equivalent additional ... IC or DoD program/project work experience. Company : VTG delivers force modernization and digital ...

Ferric

IC Product Engineer

Santa Clara, CA · On-site

$125K - $185K/yr

... power management IC's. We are seeking a dedicated hands‑on engineer with extensive proven ... Work with IC design and test teams to create and review test plans, including providing ...

Ferric

IC Product Engineer

Santa Clara, CA · On-site

$125K - $185K/yr

... power management IC's. We are seeking a dedicated hands-on engineer with extensive proven ... Work with IC design and test teams to create and review test plans, including providing ...

VTG

Test Systems Engineer

Springfield, VA · On-site

$135K - $190K/yr

Experience with test management and defect tracking tools. * Experience with traditional, Agile ... Previous IC or DoD program/project work experience. Pay Range: VTG's estimated starting pay range ...

Apple Inc.

As a power management IC designer you can also work with system engineers and architects. Together ... Review bench and production test results to drive bug fixes. * Complete designs considering ESD ...

Apple Inc.

IC Designer - Power Management

Austin, TX · On-site

As a power management IC designer you can also work with system engineers and architects. Together ... Review bench and production test results to drive bug fixes. * Complete designs considering ESD ...

Apple

IC Designer - Power Management

Austin, TX · On-site

$175K - $311K/yr

As a power management IC designer you can also work with system engineers and architects. Together ... Design with detailed testability; write test plans for trim and calibration; collaborate with test ...

Apple

IC Designer - Power Management

Austin, TX · On-site

$175K - $311K/yr

As a power management IC designer you can also work with system engineers and architects. Together ... Design with detailed testability; write test plans for trim and calibration; collaborate with test ...

MACOM

$84K - $167K/yr

... management standard. MACOM has more than 75 years of application expertise with multiple design ... IC test background. This role would be responsible for new product development from NPI stage to ...

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How much do ic test manager jobs pay per year?

As of Sep 9, 2026, the average yearly pay for ic test manager in the United States is $109,109.00, according to ZipRecruiter salary data. Most workers in this role earn between $94,000.00 and $130,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Ic Test Manager job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 11% Part Time, and 1% Contract. Highlights an 80% Physical, 2% Hybrid, and 18% Remote job distribution, with an average salary of $109,109 per year, or $52.5 per hour.

Product Development Engineer

San Jose, CA • On-site

Altera
Business Management Consulting • 1 - 5K employees
Learn more about Alteraexternal

$106K - $153K/yr

Full-time

Re-posted 10 days ago

Job description

Job Details:Job Description:

About Altera

At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industryleading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is searching for a Product Development Engineer to join our Manufacturing Content Development Engineering Group!

The Manufacturing Content Development Engineering Group is responsible for architecting, developing, validating and productizing high quality manufacturing test content for FPGAs to screen out any manufacturing defects and thus guaranteeing the highest quality of outgoing parts to customers.

Key Responsibilities:

  • Own manufacturing test content development for FPGA Reset and Configuration architectures, including Secure Device Manager (SDM), configuration interfaces, reset controllers, boot flows, and related infrastructure IPs.

  • Develop and implement DFT strategies utilizing Scan, ATPG, MBIST, IJTAG, and functional test methodologies to maximize fault coverage.

  • Perform pre-silicon test pattern simulation and validation to ensure test effectiveness prior to tape-out.

  • Collaborate with RTL, DFT, and Design Verification teams to ensure robust testability features are implemented early in the design cycle.

  • Analyze test results, debug silicon failures, and provide root cause analysis.

  • Work with manufacturing and test teams to optimize test time, cost, and quality.

  • Analyze early customer returns with emphasis on driving test hole closure activities.

  • Drive test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations.

  • Stay updated with industry trends and emerging DFT/test technologies.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based ona number offactors including job location, job-related knowledge, skills, experiences,trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$106,200- $153,675USD

We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications:

Bachelor's Degree or Master's Degree in Electrical Engineering, or related field (or other related Engineering degree) with 5+ years of industry experience in the following:

  • Experience in IC design and IC test.

  • Experience with FPGA Reset, Configuration, SDM, or DFX architectures.

  • Experience in DFT methodologies such as scan chains, Memory BIST, ATPG, boundary scan, test compression, IJTAG and JTAG networks

  • Experience with RTL design, synthesis, and verification flows.

  • Experience with fault grading, test time analysis, test coverage analysis, and test yield enhancement.

  • Scripting skills in Python, Perl, TCL, or similar.

  • Semiconductor manufacturing test processes.

  • Digital and analog circuit fundamentals.

Job Type: RegularShift:Shift 1 (United States of America)Primary Location:San Jose, California, United StatesAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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