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High Speed Analog Design Engineer Jobs (NOW HIRING)

Nokia

Senior Analog EDA/CAD ASIC Engineer

Sunnyvale, CA · On-site

$120K - $171K/yr

High-Speed Analog EDA/CAD Engineer: Brief Description: Full-time position. Infinera is seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip design in the Optical ...

Cypress HCM

Director of Analog Engineering

Johns Creek, GA · Hybrid

$180K - $309K/yr

Director of Analog Engineering This exciting role will be responsible for leading the Analog Design ... The position requires deep expertise in high-speed analog/mixed-signal design and proven leadership ...

Nokia

Senior Analog EDA/CAD ASIC Engineer

Sunnyvale, CA · On-site

$237K/yr

High-Speed Analog EDA/CAD Engineer: Brief Description: Full-time position. Infinera is seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip design in the Optical ...

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High Speed Analog Design Engineer information

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How much do high speed analog design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for high speed analog design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What is a high speed analog design engineer?

A High Speed Analog Design Engineer is a specialized electrical engineer who designs and develops analog circuits that operate at high frequencies, often for applications like telecommunications, data transmission, and signal processing. These engineers focus on creating circuits that can handle fast-changing signals with minimal distortion or loss, ensuring efficient and reliable performance. Their work typically involves the use of advanced simulation tools, PCB layout design, and testing of prototypes to meet strict speed and performance requirements.

What are the key skills and qualifications needed to thrive as a high speed analog design engineer?

To thrive as a High Speed Analog Design Engineer, you need a solid background in electrical engineering, strong expertise in analog circuit theory, and experience with high-frequency signal design. Familiarity with simulation tools like SPICE, PCB design software, and relevant industry standards or certifications (e.g., IEEE) is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set candidates apart. These skills ensure reliable, high-performance circuit designs that meet stringent requirements for speed, signal integrity, and manufacturability.

What are some typical challenges faced by high speed analog design engineers when collaborating with cross-functional teams?

High Speed Analog Design Engineers often work closely with digital designers, PCB layout specialists, and test engineers. A common challenge is ensuring that high-speed signals are properly integrated with digital systems while minimizing noise and signal integrity issues. Effective communication is crucial to align on requirements, constraints, and timelines, especially since analog and digital teams may have different priorities. Proactively participating in design reviews and maintaining clear documentation can help mitigate misunderstandings and improve overall project outcomes.

What is the difference between High Speed Analog Design Engineer vs RF Circuit Design Engineer?

AspectHigh Speed Analog Design EngineerRF Circuit Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering; circuit design certificationsBachelor's or Master's in Electrical Engineering; RF design certifications
Work EnvironmentSemiconductor companies, research labs, product developmentWireless communication firms, telecom, aerospace
Industry UsageHigh-speed data converters, amplifiers, integrated circuitsRF transceivers, antennas, wireless systems

High Speed Analog Design Engineers focus on designing circuits that operate at high frequencies with fast signal transitions, often within integrated circuits. RF Circuit Design Engineers specialize in radio frequency circuits for wireless communication, requiring expertise in RF principles. While both roles involve high-frequency circuit design, their applications and specific technical skills differ, making each role unique in the electronics industry.

What cities are hiring for High Speed Analog Design Engineer jobs?

Cities with the most High Speed Analog Design Engineer job openings:

What are popular job titles related to High Speed Analog Design Engineer jobs?

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Infographic showing various High Speed Analog Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% As Needed, 79% Full Time, 17% Part Time, 2% Contract, and 1% Nights. Highlights an 88% Physical, 1% Hybrid, and 11% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

High-Speed Analog Layout Design Engineer

Irvine, CA • On-site, Remote

Celero Communications
See more jobs at Celero Communicationsexternal

$200K - $300K/yr

Full-time

Re-posted 12 days ago

Job description

Senior/Principal High-Speed Analog Layout Design Engineer
About the Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world's most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
Key Responsibilities
•Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
•Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
•Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
•Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
•Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
•Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
•Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
Required Qualifications
•Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
•Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
•Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
•At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
•Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
•Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
•Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
•Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
•Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
•Experience working in collaborative environments with international and remote teams
•Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
•Experience using revision control systems for layout design management
Preferred Qualifications
•Exposure to optical or high-speed analog interfaces is a strong plus
•Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
•Proven ability to collaborate with international teams (U.S., Canada, Argentina)
•Strong organizational skills with high attention to detail and follow-through
•Ability to multi-task and prioritize in a fast-paced, dynamic environment
•Proactive, eager-to-learn mindset with excellent problem-solving skills
What We Offer
•The chance to play a foundational role at a high-growth semiconductor start-up
•Exposure to a wide variety of cross functional teams
•A collaborative, international team culture where ideas and initiative are valued
•The opportunity to grow alongside Celero as we scale and shape the future of our industry
•A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
Annual Base Salary Range for US: $200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
Javier Leon
Talent Acquisition
619-227-3193 cell/text
javier.leon@celero.inc
www.celero.inc

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