As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running ...
CPU Gate Level Synthesis Engineer
Santa Clara, CA · On-site
$181K - $318K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
CPU Gate Level Synthesis Engineer
Santa Clara, CA · On-site
$181K - $318K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
CPU Gate Level Synthesis Engineer
$181K - $318K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
CPU Gate Level Synthesis Engineer
$181K - $318K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
CPU Gate Level Synthesis Engineer
Santa Clara, CA · On-site
$147K - $272K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
CPU Gate Level Synthesis Engineer
Santa Clara, CA · On-site
$147K - $272K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
CPU Gate Level Synthesis Engineer
$147K - $272K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
CPU Gate Level Synthesis Engineer
$147K - $272K/yr
Description As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role ...
SoC Integration and Synthesis Engineer
Cupertino, CA · On-site
$128K - $172K/yr
... the chip level.- Work on RTL integration, timing constraints, and synthesis of designs.- Knowledge of FE flows like Lint & LEQ and scripting is a plusWork closely with other engineers that are ...
SoC Integration and Synthesis Engineer
Cupertino, CA · On-site
$128K - $172K/yr
... the chip level.- Work on RTL integration, timing constraints, and synthesis of designs.- Knowledge of FE flows like Lint & LEQ and scripting is a plusWork closely with other engineers that are ...
Timing & Synthesis Engineer
$139K - $258K/yr
... level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Execute low power physical synthesis techniques, deploying knowledge of UPF and power intent ...
Timing & Synthesis Engineer
$139K - $258K/yr
... level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Execute low power physical synthesis techniques, deploying knowledge of UPF and power intent ...
Timing & Synthesis Engineer
$139K - $258K/yr
... level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Execute low power physical synthesis techniques, deploying knowledge of UPF and power intent ...
Timing & Synthesis Engineer
$139K - $258K/yr
... level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Execute low power physical synthesis techniques, deploying knowledge of UPF and power intent ...
Timing & Synthesis Engineer
San Diego, CA · On-site
$144K - $148K/yr
... level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Logic synthesis execution (verilog RTL to netlist). Strong knowledge of the entire ASIC design ...
Timing & Synthesis Engineer
San Diego, CA · On-site
$144K - $148K/yr
... level. This is driven by a world-class vertically integrated engineering team spanning RF/Analog ... Logic synthesis execution (verilog RTL to netlist). Strong knowledge of the entire ASIC design ...
... the chip level.- Work on RTL integration, timing constraints, and synthesis of designs.- Knowledge of FE flows like Lint & LEQ and scripting is a plusWork closely with other engineers that are ...
... the chip level.- Work on RTL integration, timing constraints, and synthesis of designs.- Knowledge of FE flows like Lint & LEQ and scripting is a plusWork closely with other engineers that are ...
... level synthesis, static timing analysis, computer architecture, verification, RTL compilation ... Required : • BS in Computer Science or Electrical Engineering • Strong proficiency in C/C ...
... level synthesis, static timing analysis, computer architecture, verification, RTL compilation ... Required : • BS in Computer Science or Electrical Engineering • Strong proficiency in C/C ...
Lead Software Engineer , Synthesis
San Jose, CA · On-site
$114K - $213K/yr
Contribute to the advancement of solutions in areas such as logic synthesis, word-level synthesis ... At Cadence, you will be surrounded by hard-working, innovative engineers who thrive in a high ...
Lead Software Engineer , Synthesis
San Jose, CA · On-site
$114K - $213K/yr
Contribute to the advancement of solutions in areas such as logic synthesis, word-level synthesis ... At Cadence, you will be surrounded by hard-working, innovative engineers who thrive in a high ...
Lead Software Engineer , Synthesis
$114K - $213K/yr
Contribute to the advancement of solutions in areas such as logic synthesis, word-level synthesis ... At Cadence, you will be surrounded by hard-working, innovative engineers who thrive in a high ...
Lead Software Engineer , Synthesis
$114K - $213K/yr
Contribute to the advancement of solutions in areas such as logic synthesis, word-level synthesis ... At Cadence, you will be surrounded by hard-working, innovative engineers who thrive in a high ...
FPGA Design Eng Sr
Boulder, CO · On-site
$129K - $178K/yr
In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite, the Vitis development platform (including High-Level Synthesis), and hardware design languages VHDL ...
FPGA Design Eng Sr
Boulder, CO · On-site
$129K - $178K/yr
In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite, the Vitis development platform (including High-Level Synthesis), and hardware design languages VHDL ...
SoC Integration and Synthesis Engineer
Cupertino, CA · On-site
$147K - $272K/yr
... level. - Work on RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of ...
SoC Integration and Synthesis Engineer
Cupertino, CA · On-site
$147K - $272K/yr
... level. - Work on RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of ...
FPGA Design Eng
Boulder, CO · On-site
$129K - $178K/yr
In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite, the Vitis development platform (including High-Level Synthesis), and hardware design languages VHDL ...
FPGA Design Eng
Boulder, CO · On-site
$129K - $178K/yr
In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite, the Vitis development platform (including High-Level Synthesis), and hardware design languages VHDL ...
FPGA Design Eng Sr
Boulder, CO · On-site
$129K - $178K/yr
In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite, the Vitis development platform (including High-Level Synthesis), and hardware design languages VHDL ...
FPGA Design Eng Sr
Boulder, CO · On-site
$129K - $178K/yr
In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite, the Vitis development platform (including High-Level Synthesis), and hardware design languages VHDL ...
High Level Synthesis Engineer information
See salary details
$5.29 - $8.74
0% of jobs
$8.74 - $12.19
13% of jobs
$12.19 - $15.65
0% of jobs
$15.65 - $19.10
0% of jobs
$21.69 is the 25th percentile. Wages below this are outliers.
$19.10 - $22.55
15% of jobs
$22.55 - $26.01
19% of jobs
The median wage is $27.44 / hr.
$26.01 - $29.46
6% of jobs
$29.46 - $32.91
0% of jobs
$32.91 - $36.36
4% of jobs
$38.51 is the 75th percentile. Wages above this are outliers.
$36.36 - $39.82
28% of jobs
$39.82 - $43.27
14% of jobs
$5
$29
$43
How much do high level synthesis engineer jobs pay per hour?
As of Jun 5, 2026, the average hourly pay for high level synthesis engineer in the United States is $29.70, according to ZipRecruiter salary data. Most workers in this role earn between $21.63 and $38.46 per hour, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a High Level Synthesis Engineer, and why are they important?
To excel as a High Level Synthesis Engineer, you need a strong background in digital design, hardware description languages (HDL), and computer architecture, typically with a degree in electrical engineering or computer engineering. Proficiency with HLS tools such as Xilinx Vivado HLS or Intel HLS Compiler, along with knowledge of C/C++ and SystemC, is essential. Problem-solving, attention to detail, and effective collaboration are critical soft skills that set candidates apart. These skills ensure efficient hardware implementation, optimized performance, and successful integration with cross-functional engineering teams.
What are some common challenges faced by High Level Synthesis Engineers when translating algorithmic descriptions into hardware designs?
High Level Synthesis Engineers often encounter challenges such as optimizing hardware resource usage while maintaining performance targets when converting high-level code (like C/C++) into RTL hardware descriptions. Balancing area, speed, and power constraints requires a deep understanding of both the source algorithms and hardware architectures. Debugging and verifying the correctness of the synthesized hardware can also be complex, as issues may arise that are not present in the original software model. Collaboration with hardware and verification teams is essential to ensure the final implementation meets system requirements.
What are High Level Synthesis Engineers?
High Level Synthesis (HLS) Engineers are professionals who use specialized tools and techniques to convert high-level programming languages, such as C or C++, into hardware descriptions like VHDL or Verilog. This process allows for faster and more efficient design of digital circuits, commonly used in FPGAs and ASICs. HLS Engineers bridge the gap between software development and hardware design, optimizing algorithms for hardware implementation to meet performance, area, and power requirements. They work closely with design teams to ensure that complex systems are synthesized accurately and efficiently from high-level specifications.
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!..Apple's Silicon Engineering Group (SEG) is looking for a hardworking engineer for our CPU Gate Level Synthesis role to assess and optimize design quality. In this role, the candidate would be a part of Apple's industry-leading CPU design team, working in a multi-functional role to ensure that our CPUs meet the highest standards for performance, power and area.
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running RTL to gate level synthesis and finding opportunities to optimize timing, power, and area for micro-architectural features. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, RTL optimization and power analysis. Responsibilities include but are not limited to:• Early RTL health assessment to detect potential timing/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions• Early stage power estimation and validation for new micro-architectural features• Enhancing synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback• Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow• Partner with timing team to enable constraints generation at top levels• Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs• Track and analyze PPA trends through project cycle
Minimum BS and 3+ years of relevant industry experienceExperience in digital logic design, RTL synthesis, and physical design
The ideal candidate should ideally possess CPU implementation experienceProficiency in scripting languages (TCL, Perl, Python) for automation and flow optimizationStrong problem-solving, debugging, and collaboration skills in a fast-paced environment
As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running RTL to gate level synthesis and finding opportunities to optimize timing, power, and area for micro-architectural features. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, RTL optimization and power analysis. Responsibilities include but are not limited to:• Early RTL health assessment to detect potential timing/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions• Early stage power estimation and validation for new micro-architectural features• Enhancing synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback• Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow• Partner with timing team to enable constraints generation at top levels• Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs• Track and analyze PPA trends through project cycle
Minimum BS and 3+ years of relevant industry experienceExperience in digital logic design, RTL synthesis, and physical design
The ideal candidate should ideally possess CPU implementation experienceProficiency in scripting languages (TCL, Perl, Python) for automation and flow optimizationStrong problem-solving, debugging, and collaboration skills in a fast-paced environment
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976