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Full Time Serdes Jobs (NOW HIRING)

Hark

Signal Integrity

San Jose, CA · On-site

$120K - $300K/yr

Build channel models for SerDes links, run eye diagram analysis, and validate compliance margins ... Compensation The US base salary range for this full-time position is between $120,000 - $300,000 ...

Monarch Quantum

Firmware Engineer 4

San Diego, CA · On-site

$175K - $225K/yr

Experience with device level communication protocols (e.g., SPI, I2C, Ethernet, Serial, SerDes ... As a full-time employee, you will be eligible for Monarch's comprehensive benefits package, which ...

Micross Components

Test Engineer I

Milpitas, CA · On-site

$100K - $120K/yr

Experience with ADC, DAC, IC Temp Sensor, LVDS, SerDes, and communication interfaces (I2C, Ethernet ... Job Type: Full-time Pay: $100,000.00 - $120,000.00 per year At Micross, our Core Values of ...

BAE Systems

Eng Sr Prin II - Elec

Nashua, NH · On-site

$149K - $254K/yr

... full-time on site. **Please not that pursuant to a government contract, along with the ability to ... Experience with high-speed interfaces like PCIe, SerDes, ADC/DAC, DDR3/4 * Familiarity with ...

Lightmatter

Electrical Design Engineer

Mountain View, CA · On-site

$149K - $206K/yr

Experience with high-speed interfaces such as PCIe, DDR, Ethernet, or SerDes * Experience with ... Equity grants (applicable to full-time employees) Benefits eligibility may vary depending on your ...

Waymo

Senior Signal Integrity Engineer

Mountain View, CA · On-site

$230K - $242K/yr

SERDES, SoC Power Integrity (PI) with VR modeling, or LPDDRx interfaces * Experience in root-cause ... full-time position across US locations is listed below. Actual starting pay will be based on job ...

Arrow Electronics

Senior DFT Engineer (Einfochips)

San Jose, CA · On-site

$122K - $168K/yr

... Serdes * Tools: Mentor Tessent * B. Tech, M.Tech in Microelectronics/Electronics * Excellent ... US-CA-San Jose, California (eInfochips) Time Type: Full time Job Category: Engineering Services EEO ...

Monarch Quantum

Firmware Engineer 4

San Diego, CA · Hybrid

$175K - $225K/yr

Experience with device level communication protocols (e.g., SPI, I2C, Ethernet, Serial, SerDes ... As a full-time employee, you will be eligible for Monarch's comprehensive benefits package, which ...

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Full Time Serdes information

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$80.5K

$141.4K

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How much do full time serdes jobs pay per year?

As of Aug 23, 2026, the average yearly pay for full time serdes in the United States is $141,351.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $158,000.00 per year, depending on experience, location, and employer.

What are the most commonly searched types of Serdes jobs?

The most popular types of Serdes jobs are:

Full Time Serdes jobs near you
Infographic showing various Full Time Serdes job openings in the United States as of August 2026, with employment types broken down into 96% Full Time, and 4% Contract. Highlights an 86% Physical, 7% Hybrid, and 7% Remote job distribution, with an average salary of $141,351 per year, or $68 per hour.

Signal Integrity

Hark

San Jose, CA • On-site

$120K - $300K/yr

Full-time

Re-posted 7 days ago

Job description

About Hark
Hark is an artificial intelligence company building advanced, personalized intelligence. One that is proactive, multimodal, and capable of interacting with the world through speech, text, vision, and persistent memory.
We're pairing that intelligence with next-generation hardware to create a universal interface between humans and machines. While today's AI largely operates through chat boxes and decade-old devices, Hark is focused on what comes next: agentic systems that interact naturally with people and the real world.
To get there, we're developing multimodal models and next-generation AI hardware together - designed from the ground up as a single, unified interface for a new era of intelligent systems.
About the Role
We're looking for a Signal Integrity Engineer to join our hardware team and help ensure our AI-powered devices perform flawlessly at the electrical level. In this role, you'll own SI analysis across high-speed interfaces - DDR, PCIe, USB, MIPI - and work closely with our PCB layout, ASIC, and mechanical design teams to solve the unique challenges that come with packing serious compute into compact, thermally constrained form factors. You'll run simulations, validate designs in the lab, and feed findings back into our design rules as we scale from prototypes to volume production.
Responsibilities
  • SI Analysis: Perform pre-layout and post-layout signal integrity simulations for high-speed interfaces (DDR4/5, PCIe Gen3/4, USB 3.x, MIPI CSI/DSI).
  • PI Analysis: Model and optimize power distribution networks (PDN), including decoupling strategies, plane resonance, and target impedance.
  • Channel Modeling: Build channel models for SerDes links, run eye diagram analysis, and validate compliance margins.
  • PCB Stackup: Define PCB stackup, impedance profiles, and routing constraints in collaboration with layout engineers.
  • Lab Validation: Conduct bench-level measurements using oscilloscopes, VNAs, TDR, and spectrum analyzers to correlate simulation with hardware.
  • EMI/EMC: Identify and mitigate electromagnetic interference issues at the board and system level, supporting regulatory certification.
  • Design Rules: Develop and maintain SI/PI design guidelines and constraint sets for the hardware team.

Requirements
  • Education: BS/MS in Electrical Engineering with a focus on electromagnetics, RF, or signal integrity.
  • Tool Proficiency: Hands-on experience with SI/PI tools such as Ansys HFSS, Keysight ADS/PathWave, Cadence Sigrity, or Simbeor.
  • High-Speed Interfaces: Deep working knowledge of DDR, PCIe, USB, and/or MIPI signaling standards and compliance testing.
  • Lab Skills: Expert-level skills with high-bandwidth oscilloscopes, VNAs, TDR equipment, and near-field EMI probes.
  • PCB Knowledge: Strong understanding of multi-layer PCB fabrication, materials (Dk/Df), and controlled-impedance routing.

Bonus Qualifications
  • Experience with LPDDR5 or high-speed memory interfaces on mobile/edge compute platforms.
  • Background in RFIC or antenna design for Wi-Fi, Bluetooth, or UWB systems.
  • Familiarity with 3D electromagnetic solvers for package-level or connector modeling.
  • Experience supporting EMC certification (FCC, CE, VCCI) from design through test.

Compensation
The US base salary range for this full-time position is between $120,000 - $300,000 annually.
The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended.

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