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Full Time Serdes Jobs (NOW HIRING)

W3Global Inc.

Senior FPGA Engineer

Manchester, NH · On-site

$140K - $170K/yr

Experience Required * 10+ years of experience * Full-Time * Onsite role Key Responsibilities ... High-speed data transmission (SERDES, DDR, LVDS) * Hardware integration, debugging, and testing ...

Picarro, Inc

Senior Engineer, FPGA

Santa Clara, CA · On-site

$170K/yr

Familiarity with high-speed interfaces such as PCIe, DDR, Ethernet, Aurora, JESD204, or SerDes ... The base salary range for this full-time position is $ 160 K to $170K. Our total compensation ...

Picarro, Inc

Senior Engineer, FPGA

Santa Clara, CA

$170K/yr

Familiarity with high-speed interfaces such as PCIe, DDR, Ethernet, Aurora, JESD204, or SerDes ... The base salary range for this full-time position is $ 160 K to $170K. Our total compensation ...

MatX

Optical Network Engineer

Mountain View, CA

$175K - $362K/yr

Deep knowledge of PAM4 signal theory, SerDes architecture, and optical link physics at 200G per ... this full-time position is determined based on a variety of factors including role, experience ...

E-Space

Digital Design Engineer

Saratoga, CA

$130K - $225K/yr

Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... a year This is a full time, exempt position, based out of our Saratoga office. The total ...

E-Space

Digital Design Engineer

Saratoga, CA · On-site

$130K - $225K/yr

Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... FPGA vendor toolchains (for interface bring-up and debug) This is a full time, exempt position ...

E-Space

Digital Design Engineer

Saratoga, CA · On-site

$130K - $225K/yr

Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... a year This is a full time, exempt position, based out of our Saratoga office. The total ...

MatX

Optical Network Engineer

Mountain View, CA · On-site

$175K - $362K/yr

Deep knowledge of PAM4 signal theory, SerDes architecture, and optical link physics at 200G per ... this full-time position is determined based on a variety of factors including role, experience ...

United Airlines

Electrical Engineer

Santa Clara, CA · On-site

$68K - $161K/yr

Work on high-speed interfaces such as PCIe, DDR, Ethernet, USB, and SerDes. * Review signal ... Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

... (8+ years) for permanent , full-time , onsite roles in Silicon Valley supporting advanced ... Ethernet (802.3), MAC / PCS / SerDes / PHY * High-speed designs (100G+ preferred) * Tapeout ...

United Airlines

Analog Layout Engineer

San Francisco, CA

$238K/yr

Proven experience with analog floor planning and layout for complex modules such as SerDes, ADC/DAC ... Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time ...

United Airlines

Analog Layout Engineer

Santa Clara, CA

$237K/yr

Proven experience with analog floor planning and layout for complex modules such as SerDes, ADC/DAC ... Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time ...

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Full Time Serdes information

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$141.4K

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How much do full time serdes jobs pay per year?

As of Aug 14, 2026, the average yearly pay for full time serdes in the United States is $141,351.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $158,000.00 per year, depending on experience, location, and employer.

What are the most commonly searched types of Serdes jobs?

The most popular types of Serdes jobs are:

Full Time Serdes jobs near you
Infographic showing various Full Time Serdes job openings in the United States as of August 2026, with employment types broken down into 96% Full Time, and 4% Contract. Highlights an 86% Physical, 7% Hybrid, and 7% Remote job distribution, with an average salary of $141,351 per year, or $68 per hour.

Senior/Principal Engineer with Signal/Power Integrity, Multiphysics, PDK/ADK Experience

Nityo Infotech

Austin, TX • On-site

$165K/yr

Full-time

Re-posted 4 days ago

Job description

Role: Senior/Principal Engineer with Signal/Power Integrity, Multiphysics, PDK/ADK Experience

Location: Austin, TX (HYBRID)

Job Type: FULL TIME

MUST HAVE: SI/PI - Signal Integrity /Power Integrity, Multiphysics simulations, Advanced packaging, Heterogeneous integration platforms, multi-material packages, PDK/ADK simulation collateral Experience

Job Description:

What You’ll Do

  • Own and execute hands-on SI/PI and multiphysics simulations for advanced 2.5D/3.0D heterogeneous integration and multi-material packages.
  • Perform modeling, extraction, and verification of high-speed interconnects, power delivery networks, thermal management, and mechanical stress across chiplets and advanced substrates.
  • Build and validate comprehensive ADK/PDK models (electrical, EM, thermal, mechanical) that accurately represent package-level behavior and enable system-level co-design.
  • Run end-to-end simulation workflows including EM extraction, S-parameter generation, PDN impedance analysis, crosstalk/eye diagram simulations, thermal/structural reliability checks, and co-simulation across domains.
  • Collaborate directly with EDA vendors (Cadence, Ansys, Synopsys, Siemens, Keysight, etc.), OSATs, and foundries to develop, test, and refine package simulation flows.
  • Generate user guides, reference flows, scripts, and automation that make SI/PI/multiphysics enablement repeatable and accessible to design teams.
  • Stay current with next-gen interface standards (PCIe Gen6/7, CXL, UCIe, UALink, SerDes, HBM) and incorporate their requirements into package design methodologies.
  • Guide technical strategy for SI/PI flows, mentor junior engineers, and represent TIE in working groups, customer design reviews, and industry forums.

Required Qualifications:

  • BS in Electrical Engineering, Computer Engineering, Applied Physics, or related discipline.
  • 8+ years (Senior) / 12+ years (Principal) of direct, hands-on experience in signal integrity, power integrity, and multiphysics simulations for advanced packaging, 2.5D/3DIC, or heterogeneous integration platforms.
  • Strong expertise with EDA/EM/multiphysics tools: Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Synopsys RaptorX, Siemens HyperLynx, Keysight ADS, COMSOL, CST Studio.
  • Proven ability to extract/package-level models (RLC, S-parameters, dielectric/thermal constants, warpage/stress data) and integrate them into design enablement flows.
  • Demonstrated experience creating and validating PDK/ADK simulation collateral spanning SI/PI, RF, thermal, and mechanical domains.
  • Hands-on scripting/automation skills (Python, Tcl, SKILL, etc.) to streamline simulation flows.
  • Startup DNA. You’re energized by ambiguity, act with urgency, and take personal ownership for outcomes. You make things happen.
  • Execution mindset. You have demonstrated experience working in a hands-on role driving progress across multiple initiatives without layers of management.
  • Location. Austin, Texas is preferred for close collaboration with our engineering teams and partners. Hybrid work arrangements may be possible with travel up to 30–50%.  Such arrangements are subject to University review and approval in relation to jurisdictional employment-related laws, rules, and regulations.

Preferred Qualifications:

  • MS or PhD in Electrical Engineering, Applied Physics, or related discipline.
  • Deep experience with multi-material packages (Si, glass, organics, Cu, RDL, TSV, hybrid bonding, etc.).
  • Expertise in system-level co-simulation spanning electrical, thermal, and mechanical domains for high-power/high-bandwidth-density packages.
  • Familiarity with industry standards (IEEE, JEDEC, OIF, UCIe, 3Dblox, JEP30) and experience contributing to working groups.
  • Background in high-speed interconnect modeling and compliance testing for PCIe, CXL, UCIe, SerDes, HBM, or similar standards.
  • Track record of technical publications, patents, or open-source contributions in SI/PI/multiphysics simulation and design enablement.