NXP's Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs. Our team is part of the Design Enablement/Foundation IP ...
NXP's Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs. Our team is part of the Design Enablement/Foundation IP ...
NXP's Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs. Our team is part of the Design Enablement/Foundation IP ...
NXP's Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs. Our team is part of the Design Enablement/Foundation IP ...
Associate Design Engineer
San Luis Obispo, CA · On-site
$71K - $80K/yr
As an Associate Design Engineer, you'll work on front drivetrain components used by elite cyclists ... At SRAM, we believe in expanding the potential of cycling, and that starts with you. KEY ...
Associate Design Engineer
San Luis Obispo, CA · On-site
$71K - $80K/yr
As an Associate Design Engineer, you'll work on front drivetrain components used by elite cyclists ... At SRAM, we believe in expanding the potential of cycling, and that starts with you. KEY ...
Senior SRAM Layout Design Engineer - Equity Eligible (Santa Clara)
Santa Clara, CA · On-site
$124K - $195K/yr
A leading technology company in California is seeking a Senior Layout Mask Design Engineer to work on custom SRAM designs using advanced FinFET technologies. The ideal candidate will have over 8 ...
Senior SRAM Layout Design Engineer - Equity Eligible (Santa Clara)
Santa Clara, CA · On-site
$124K - $195K/yr
A leading technology company in California is seeking a Senior Layout Mask Design Engineer to work on custom SRAM designs using advanced FinFET technologies. The ideal candidate will have over 8 ...
Overview of Role We are seeking a highly talented and motivated Senior Memory Design Engineer with deep expertise in SRAM and memory compiler development to join our innovative team. As a Senior ...
Overview of Role We are seeking a highly talented and motivated Senior Memory Design Engineer with deep expertise in SRAM and memory compiler development to join our innovative team. As a Senior ...
Memory Design Engineer
Troy, MI · On-site
Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations. * Exposure to full embedded memory design flow: Architecture, circuit design, physical ...
Quick apply
Memory Design Engineer
Troy, MI · On-site
Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations. * Exposure to full embedded memory design flow: Architecture, circuit design, physical ...
Senior SRAM Engineer
Santa Clara, CA · On-site
Design best-in-class SRAM circuits using state-of-the-art technology processes * Optimize circuits ... Engineering * Minimum 12 years of circuit design experience * Strong understanding of SRAM and ...
New
Senior SRAM Engineer
Santa Clara, CA · On-site
Design best-in-class SRAM circuits using state-of-the-art technology processes * Optimize circuits ... Engineering * Minimum 12 years of circuit design experience * Strong understanding of SRAM and ...
New
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Engineer your future. We empower our employees to truly own their career and development. Come ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Engineer your future. We empower our employees to truly own their career and development. Come ...
Exposure to complete design cycle of SRAM memory and compiler development * Supervise layout engineers and review layout for optimality * Have the ability to come up with comprehensive design ...
Exposure to complete design cycle of SRAM memory and compiler development * Supervise layout engineers and review layout for optimality * Have the ability to come up with comprehensive design ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$120 - $180/hr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... Experience in C or C++ programming * Experience using an interpretive language such as Perl or ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$120 - $180/hr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... Experience in C or C++ programming * Experience using an interpretive language such as Perl or ...
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
SRAM design, Register Files and Memory Compilers * High Speed serial and/or Parallel IOs * Sub ... Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 ...
SRAM design, Register Files and Memory Compilers * High Speed serial and/or Parallel IOs * Sub ... Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 ...
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... with SRAM design is also a plus * Hands-on experience with NVM test chip design, bring-up, and ...
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... with SRAM design is also a plus * Hands-on experience with NVM test chip design, bring-up, and ...
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Circuit Design Automation Engineer
Austin, TX · On-site
$180 - $260/hr
As a Custom Design Automation engineer for digital design team, you will perform the following ... Define and develop QA checks to verify EDA views of SRAM and register files. * Collaborate with ...
Circuit Design Automation Engineer
Austin, TX · On-site
$180 - $260/hr
As a Custom Design Automation engineer for digital design team, you will perform the following ... Define and develop QA checks to verify EDA views of SRAM and register files. * Collaborate with ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Freelance Sram Design Engineer information
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$23.52 is the 25th percentile. Wages below this are outliers.
$14.90 - $25.57
31% of jobs
The median wage is $32.14 / hr.
$25.57 - $36.23
31% of jobs
$36.23 - $46.90
4% of jobs
$56.23 is the 75th percentile. Wages above this are outliers.
$46.90 - $57.56
10% of jobs
$57.56 - $68.23
9% of jobs
$68.23 - $78.89
5% of jobs
$78.89 - $89.55
0% of jobs
$89.55 - $100.22
8% of jobs
$100.22 - $110.88
0% of jobs
$110.88 - $121.55
0% of jobs
$121.55 - $132.21
1% of jobs
$14
$47
$132
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SRAM/ROM Circuit Design Engineer
Austin, TX • On-site
Full-time
Posted 15 days ago
Job description
Our team is part of the Design Enablement/Foundation IP organization within the Chief Technology Office at NXP. We provide differentiating SRAM/ROM memory compiler solutions to NXP SoC design teams across multiple business lines- your work will have real impact for our design teams and, through them, our end products and end customers.
Job Summary:
- Implement design of CMOS memory circuits to meet memory compiler performance, power, and area requirements, including periphery circuits to support functional safety and scan functionality.
- Generate, execute, and evaluate simulation characterization measurements and simulation test benches, and compare vs. performance targets/benchmarks.
- Engage with layout teams on implementation of compiler leaf cells based on designs to improve area and performance.
- Work closely with CAD teams on implementation of new designs into our characterization, verification, and regression flows.
- Align with modeling/verification team to ensure consistency of designs with frontend models (behavioral/ATPG/emulation).
- Collaborate effectively across global memory teams to help ensure common methodologies and best practices.
- Leverage internally supported LLM/GenAI tools and EDA vendor GenAI solutions to implement efficiencies in design methodologies.
Job Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline. (Master's degree is preferred).
- 8+ years of industry experience (6+ with Master's degree) in SRAM memory circuit design, including some design experience with advanced CMOS foundry technologies at 5nm and beyond.
- Strong familiarity with Cadence Virtuoso and other industry-standard EDA tools.
- Familiarity with automotive design rules and memory design requirements is a plus.
- Good knowledge of scripting languages such as Perl, tcl, or Python is a must.
- Creative mindset, with strong analytical and problem-solving skills.
Job location:
- The position will be based at the NXP offices in Austin, Texas. Team members are expected to work in office at least 3 days/week.
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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