Principal FPGA Engineer
$129K - $157K/yr
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators) * Demonstrated ability to lead successful teams. * Experience managing technical, cost, and schedule risks and opportunities.
$129K - $157K/yr
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators) * Demonstrated ability to lead successful teams. * Experience managing technical, cost, and schedule risks and opportunities.
$129K - $157K/yr
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators) * Demonstrated ability to lead successful teams. * Experience managing technical, cost, and schedule risks and opportunities.
Mckinney, TX · On-site
$129K - $157K/yr
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators) * Demonstrated ability to lead successful teams. * Experience managing technical, cost, and schedule risks and opportunities.
Mckinney, TX · On-site
$129K - $157K/yr
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators) * Demonstrated ability to lead successful teams. * Experience managing technical, cost, and schedule risks and opportunities.
Manhattan, NY · On-site
$100 - $125/hr
Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt ... As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our ...
Manhattan, NY · On-site
$100 - $125/hr
Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt ... As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our ...
Mckinney, TX · On-site
$129K - $157K/yr
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators) * Demonstrated ability to lead successful teams. * Experience managing technical, cost, and schedule risks and opportunities.
Mckinney, TX · On-site
$129K - $157K/yr
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators) * Demonstrated ability to lead successful teams. * Experience managing technical, cost, and schedule risks and opportunities.
Manhattan, NY · On-site
$250/hr
As an inference research engineer on HAIL, you will have a general mandate to improve all aspects ... CUDA Graphs, FPGA/ASIC experience * Must have two or more years work experience building deep ...
Manhattan, NY · On-site
$250/hr
As an inference research engineer on HAIL, you will have a general mandate to improve all aspects ... CUDA Graphs, FPGA/ASIC experience * Must have two or more years work experience building deep ...
Fremont, CA · On-site
$200 - $250/hr
Processing-element and dataflow architecture for Edge 1 * FPGA validation before ASIC implementation * Instruction-set and compiler co-design * Transformer-native inference architecture
Fremont, CA · On-site
$200 - $250/hr
Processing-element and dataflow architecture for Edge 1 * FPGA validation before ASIC implementation * Instruction-set and compiler co-design * Transformer-native inference architecture
We are seeking a Business Development Manager to drive growth in FPGA-based solutions across the ... Edge AI and on-device inference (model deployment, quantization, AI acceleration) * Multi-sensor ...
We are seeking a Business Development Manager to drive growth in FPGA-based solutions across the ... Edge AI and on-device inference (model deployment, quantization, AI acceleration) * Multi-sensor ...
We are seeking a Business Development Manager to drive growth in FPGA-based solutions across the ... Edge AI and on-device inference (model deployment, quantization, AI acceleration) * Multi-sensor ...
We are seeking a Business Development Manager to drive growth in FPGA-based solutions across the ... Edge AI and on-device inference (model deployment, quantization, AI acceleration) * Multi-sensor ...
Merrifield, VA · On-site
$100 - $125/hr
Job Summary Logos is searching for an FPGA developer to join a multidisciplinary team implementing ... Implementing AI/ML inference algorithms using Vitis AI * Linux device driver development * Bit ...
Merrifield, VA · On-site
$100 - $125/hr
Job Summary Logos is searching for an FPGA developer to join a multidisciplinary team implementing ... Implementing AI/ML inference algorithms using Vitis AI * Linux device driver development * Bit ...
San Jose, CA · On-site
$150K - $275K/yr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling ...
San Jose, CA · On-site
$150K - $275K/yr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling ...
San Jose, CA · On-site
$150K - $275K/yr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling ...
Quick apply
San Jose, CA · On-site
$150K - $275K/yr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling ...
San Jose, CA · On-site
$150 - $200/hr
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
San Jose, CA · On-site
$150 - $200/hr
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
San Jose, CA · On-site
$105K/yr
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
San Jose, CA · On-site
$105K/yr
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
San Jose, CA · On-site
$125 - $150/hr
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
San Jose, CA · On-site
$125 - $150/hr
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
San Jose, CA · On-site
$76 - $99.50/hr
Architect clocking solutions for FPGA-based and SoC-integrated ML/AI inference and training accelerator pipelines, including matrix multiply units, systolic arrays, and vector processing engines.
San Jose, CA · On-site
$76 - $99.50/hr
Architect clocking solutions for FPGA-based and SoC-integrated ML/AI inference and training accelerator pipelines, including matrix multiply units, systolic arrays, and vector processing engines.
San Jose, CA · On-site
Architect clocking solutions for FPGA-based and SoC-integrated ML/AI inference and training accelerator pipelines, including matrix multiply units, systolic arrays, and vector processing engines.
San Jose, CA · On-site
Architect clocking solutions for FPGA-based and SoC-integrated ML/AI inference and training accelerator pipelines, including matrix multiply units, systolic arrays, and vector processing engines.
San Jose, CA · Hybrid
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
San Jose, CA · Hybrid
Implement and optimize AI inference solutions on FPGA SoCs, NPUs, and GPUs, balancing performance, latency, power consumption, and resource utilization. * Research and prototype innovative solutions ...
Job Summary Logos is searching for an FPGA developer to join a multidisciplinary team implementing ... Implementing AI/ML inference algorithms using Vitis AI * Linux device driver development * Bit ...
Job Summary Logos is searching for an FPGA developer to join a multidisciplinary team implementing ... Implementing AI/ML inference algorithms using Vitis AI * Linux device driver development * Bit ...
Fairfax, VA · On-site
Job Summary Logos is searching for an FPGA developer to join a multidisciplinary team implementing ... Implementing AI/ML inference algorithms using Vitis AI * Linux device driver development * Bit ...
Fairfax, VA · On-site
Job Summary Logos is searching for an FPGA developer to join a multidisciplinary team implementing ... Implementing AI/ML inference algorithms using Vitis AI * Linux device driver development * Bit ...
Austin, TX · On-site
$152K/yr
Understanding of FPGA-based acceleration and hardware/software co-design methodologies. * Experience with AI inference deployment using ONNX, PyTorch, TensorFlow, or related frameworks. * Experience ...
Austin, TX · On-site
$152K/yr
Understanding of FPGA-based acceleration and hardware/software co-design methodologies. * Experience with AI inference deployment using ONNX, PyTorch, TensorFlow, or related frameworks. * Experience ...
$85K - $95.3K
1% of jobs
$95.3K - $105.6K
4% of jobs
$105.6K - $116K
6% of jobs
$116K - $126.3K
9% of jobs
$128.4K is the 25th percentile. Wages below this are outliers.
$126.3K - $136.6K
23% of jobs
The median wage is $141.4K / yr.
$136.6K - $146.9K
14% of jobs
$146.9K - $157.2K
10% of jobs
$163.2K is the 75th percentile. Wages above this are outliers.
$157.2K - $167.5K
14% of jobs
$167.5K - $177.9K
11% of jobs
$177.9K - $188.2K
5% of jobs
$188.2K - $198.5K
3% of jobs
$85K
$147.3K
$198.5K
Other pages related to Fpga Inference:

Mckinney, TX
$129K - $157K/yr
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Re-posted 6 days ago
8.2
Based on 86 frontline employees who took The Breakroom Quiz
38th of 72 rated aerospace companies
Date Posted:
2026-07-17Country:
United States of AmericaLocation:
US-TX-MCKINNEY-513WD ~ 2501 W University Dr ~ WING D BLDGPosition Role Type:
OnsiteU.S. Citizen, U.S. Person, or Immigration Status Requirements:
The ability to obtain and maintain a U.S. government issued security clearance is required. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearanceSecurity Clearance Type:
DoD Clearance: SecretSecurity Clearance Status:
Active and existing security clearance required after day 1At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.
The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment.
We are currently seeking a Principal Electrical Engineer, with strong technical leadership ability, to function as the Field Programmable Gate Array Lead.
This position is an onsite role, located in McKinney, TX.
What you will do
Provide full lifecycle support of production quality FPGA designs for all major vendors and device families including AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
Generate FPGA designs for the following applications: gigabit and multigigabit transceiver (MGT) serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.
Translate system level requirements into FPGA requirements
Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)
Lead small teams of FPGA engineers and code in VHDL for reliability and maintainability
Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage
Define schedules for FPGA tasking and drive execution to the planned budget and schedule.
Identify and manage project risks and opportunities.
Create complete documentation including requirements, verification plan, and user’s guides
Lead medium sized teams to success.
Coach, review, and delegate work to junior engineers.
Serve as a subject-matter expert within discipline.
Lead internal and external technical reviews.
Support customer interactions and relations.
Contribute to product and technology roadmaps
Make improvements to processes, systems or products to enhance overall performance
Engage in personal technical growth and facilitate technical growth in peers and junior engineers.
Qualifications You Must Have
Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experience.
Experience to include one or more of the following:
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
Hands on experience with integration and debug of FPGA/ASIC in a lab environment
Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
Experience with source code management, design reviews, and code release in a team development environment.
Qualifications We Value
One or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major. A suitable degree may be counted as 2 years of work experience.
FPGA/ASIC design experience in one or more of the following areas:
Radar processing techniques
Image processing techniques for visual and infrared sensors
Embedded systems design using ARM, Microblaze, or NIOS processors
Gigabit serial interfaces and multi-gigabit transceivers (MGTs)
Constrained random verification in UVM using System Verilog
Verification utilizing emulation platforms, such as Veloce
Experience with High Level Synthesis (HLS)
Experience with vector processors and/or GPUs
Using AI to improve FPGA workflows (verification automation, log triage, regression analytics)
AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators)
Demonstrated ability to lead successful teams.
Experience managing technical, cost, and schedule risks and opportunities.
Experience with project management tools such as Earned Value and/or Agile Execution.
Experience communicating and documenting technical topics and presenting to customers and management.
Experience leading a program transition from development to production.
Proposal development experience.
Experience with intellectual property generation (patents & publications).
Demonstrated mentorship of junior engineers.
What We Offer
Our values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.
This position offers relocation based on candidate eligibility.
Learn More & Apply Now!
This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website
here: https://www.state.gov/m/ds/clearances/c10978.htm
gov/m/ds/clearances/c10978.htm
North Texas: https://careers.rtx.com/global/en/raytheon-north-texas-location
#LI-CV1
As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.
The salary range for this role is 107,500 USD - 204,500 USD. The salary range provided is a good faith estimate representative of all experience levels. RTX considers several factors when extending an offer, including but not limited to, the role, function and associated responsibilities, a candidate’s work experience, location, education/training, and key skills. Hired applicants may be eligible for benefits, including but not limited to, medical, dental, vision, life insurance, short-term disability, long-term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, Employee Scholar Program, parental leave, paid time off, and holidays. Specific benefits are dependent upon the specific business unit as well as whether or not the position is covered by a collective-bargaining agreement. Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement. Payments under these annual programs are not guaranteed and are dependent upon a variety of factors including, but not limited to, individual performance, business unit performance, and/or the company’s performance. This role is a U.S.-based role. If the successful candidate resides in a U.S. territory, the appropriate pay structure and benefits will apply. RTX anticipates the application window closing approximately 40 days from the date the notice was posted. However, factors such as candidate flow and business necessity may require RTX to shorten or extend the application window.RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status, or any other applicable state or federal protected class. RTX provides affirmative action in employment for qualified Individuals with a Disability and Protected Veterans in compliance with Section 503 of the Rehabilitation Act and the Vietnam Era Veterans’ Readjustment Assistance Act.
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Guided missile and space vehicle manufacturing, it services, aerospace product and parts manufacturing and engineering professional services
10,000+ Employees
Waltham, MA, US