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Formal Design Verification Engineer Jobs (NOW HIRING)

Baidu USA

Design Verification Engineer

Sunnyvale, CA

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... Formal Verification (Model Checking, Equivalence Checking). * Excellent communication skills in ...

COGENT Infotech

Design Verification Engineer

Saratoga, CA · On-site

$150K - $183K/yr

Design Verification Engineer Location: Saratoga, CA (Onsite)-5 days We are seeking a Design Verification Engineer with 8+ years of experience in semiconductor verification. The ideal candidate will ...

Purple Hires Inc

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate. Drive ...

Texas Instruments

Design Verification Engineer

Dallas, TX · On-site

$135K - $164K/yr

Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Dallas. In this role, you will develop and execute verification strategies that ensure ...

Cirrus Logic

Design Verification Engineer

Chandler, AZ · On-site

$133K - $163K/yr

We are seeking an experienced and innovative Design Verification Engineer to join a world-class ... Formal verification * Hardware emulation or acceleration * Software-driven verification

Dexian

Formal Verification Engineer

Sunset, TX · On-site

$122K/yr

Formal Verification Engineer Austin, TX 12 + Months Role ... Lead design verification using formal tools and spec analysis. Must Have: VC Formal or JasperGold ...

Texas Instruments

Design Verification Engineer

Knoxville, TN · On-site

$129K - $158K/yr

Love your job. Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Knoxville. In this role, you will develop and execute verification ...

Texas Instruments Incorporated

$100K - $122K/yr

Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Dallas. In this role, you will develop and execute verification strategies that ensure ...

Broadcom Inc.

Design Verification Engineer

Broomfield, CO · On-site

$108K - $172K/yr

Design Verification Engineer Broadcom's ASIC Products Division (APD) is looking for an experienced ... Formal verification concepts/experience. * Verifying iJTAG network using ICL and PDL in the Tessent ...

Texas Instruments

$126K - $154K/yr

Texas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Dallas. In this role, you will develop and execute verification strategies that ensure ...

Apple

Formal Verification Engineer

Austin, TX · On-site

$134K/yr

As part of our Silicon Technologies group, you'll help design and manufacture our next-generation ... Description As a formal verification engineer working the complete formal verification for single ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

You will work closely with architects, design engineers, software teams, and verification ... Formal Verification * Emulation platforms (Veloce/Palladium/ZeBu) * Power-aware verification

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Formal Design Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do formal design verification engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for formal design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Formal Design Verification Engineer jobs?

For Formal Design Verification Engineer jobs, the most frequently searched job titles are:

Senior Design Verification Engineer

Austin, TX

Correct Designs
11 - 50 employees
Learn more about Correct Designsexternal

$134K - $164K/yr

Contractor

Medical, Retirement

Re-posted 28 days ago

Job description

Current Openings >> Senior Design Verification Engineer
Senior Design Verification Engineer
Summary
Title: Senior Design Verification Engineer ID: 1064 Location: Austin, TX
More about this job >
Description

Senior Design Verification Engineer

Looking for new challenges?  Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs.  

Correct Designs is NOT the typical contracting, staff augmentation firm.  Our engineers have respected long term roles with generous hourly rates in excellent team environments.  A typical contract may last 3 years, although we have shorter and even longer term work available. We are well respected in the Design Verification community with clients always seeking new CDI engineers. If you need a few months off between contracts you can take that break and know there will be plenty of work available when you return.  If you like the stability of always working, simply move to the next contract with little time off. Correct Designs does provide health care and retirement plan benefits.

We are based in Austin, Texas with clients throughout the US.  There are opportunities for both in-person and remote work. 
Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career.  
Correct Designs uses E-Verify to confirm work status eligibility.
 

RESPONSIBILITIES:

  • Verify complex design blocks using equally complex SV/UVM verification environments
  • Develop and execute pre-silicon verification test plans
  • Develop directed and random verification tests to validate block and IP functionality
  • Develop verification components and tools
  • Develop verification functional coverage using industry standard coverage analysis tools/methods
  • Debug regression fails 
  • Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

 REQUIRED SKILLS AND EXPERIENCE:

  • 8 or more years of proven verification experience in a hardware development setting
  • Strong background in SystemVerilog and UVM verification methodologies
  • Strong debug skills and experience with debug tools such as DVE/Verdi
  • Proficiency in Object Oriented programming, computer architecture and data structures
  • Strong analytical/problem solving skills and pronounced attention to details
  • Strong interpersonal and communication skills
  • Must be comfortable working across geographies

DESIRED SKILLS:

  • Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
  • Experience in other related domains such as formal verification, RTL design, or software development

 EDUCATION:

Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science

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