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Flex Work From Home Dft Engineer Jobs (NOW HIRING)

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Tenstorrent

DFT Engineer

Santa Clara, CA · On-site +1

$100K - $500K/yr

You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries ... differ from the one in this posting. Who you are * You have a Bachelor's, Master's, or PhD in ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

K2 Space

Senior DFT Engineer

$170K - $250K/yr

Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe ... The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and ...

Sapsol Technologies Inc

Lead ASIC DFT Engineer

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ... Strong communication skills and the ability to work independently with minimal ramp-up.

Next Step Systems

FPGA Engineer - Work From Home

Chicago, IL · On-site +1

$133K - $172K/yr

FPGA Engineer - Work From Home We are seeking a talented and self-motivated FPGA Engineer to join a growing hardware engineering team. Our culture emphasizes teamwork and focuses on continuous ...

AO Globe Life

Work From Home

Virginia Beach, VA · On-site +1

Join our fully virtual, work-from-home team where you can earn an exceptional income while still cherishing every precious moment with your loved ones. With the freedom to set your own hours, you can ...

AO Globe Life

Work From Home

Virginia Beach, VA · On-site +1

Join our fully virtual, work-from-home team where you can earn an exceptional income while still cherishing every precious moment with your loved ones. With the freedom to set your own hours, you can ...

The Jernigan Agency

WORK FROM HOME

Hartford, CT · On-site +1

Occasional travel for work for in-person conferences. If you are not currently licensed but have a desire to learn this business, we will help guide you in that process. Sales * Call on our lead ...

AO Globe Life

Work From Home

Virginia Beach, VA · On-site +1

Join our fully virtual, work-from-home team where you can earn an exceptional income while still cherishing every precious moment with your loved ones. With the freedom to set your own hours, you can ...

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Flex Work From Home Dft Engineer information

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$59K

$137.3K

$196.5K

How much do flex work from home dft engineer jobs pay per year?

As of Aug 24, 2026, the average yearly pay for flex work from home dft engineer in the United States is $137,309.00, according to ZipRecruiter salary data. Most workers in this role earn between $101,500.00 and $196,000.00 per year, depending on experience, location, and employer.

What is a flex work from home DFT engineer?

A Flex Work From Home DFT (Design for Test) Engineer is a specialized hardware engineer who focuses on designing and implementing testability features in integrated circuits (ICs), while having the flexibility to work remotely. Their role involves ensuring that chips can be effectively tested for faults during manufacturing and later use. Working flexibly from home means they may have adjustable hours and collaborate with teams across different locations, often using remote communication and design tools. This setup allows for a better work-life balance while still contributing to the development of reliable, testable semiconductor products.

What are the key skills and qualifications needed to thrive as a flex work from home DFT engineer?

To thrive as a Flex Work From Home DFT (Design for Test) Engineer, you need a strong background in digital design, test methodologies, and a degree in electrical or computer engineering. Proficiency with EDA tools like Synopsys, Mentor Graphics, or Cadence, and familiarity with scripting languages such as Python or TCL, are typically required, along with relevant certifications. Excellent problem-solving, communication, and time management skills are crucial for effective remote collaboration and project delivery. These skills ensure robust test architecture, efficient debugging, and seamless teamwork, which are vital for delivering high-quality silicon products on schedule.

What are some common challenges faced by flex work from home DFT engineers, and how can they be managed?

Flex Work From Home DFT (Design for Test) Engineers often face challenges related to remote collaboration and access to specialized hardware or lab equipment. Communication with cross-functional teams, like design and verification engineers, can be more complex when working remotely, making it vital to use collaboration tools effectively and maintain clear documentation. Additionally, troubleshooting and validating test methodologies may require creative solutions or remote access protocols. Proactively scheduling regular check-ins and leveraging cloud-based simulation environments can help overcome these challenges and ensure smooth project progress.

What is the difference between Flex Work From Home Dft Engineer vs Flex Work From Home PCB Design Engineer?

AspectFlex Work From Home Dft EngineerFlex Work From Home PCB Design Engineer
Required CredentialsBachelor's in Electronics/Telecom, DFT certificationsBachelor's in Electronics/Computer Engineering, PCB design certifications
Work EnvironmentRemote, collaborative with manufacturing teamsRemote, focused on design software and collaboration
Industry UsageTelecom, electronics manufacturingElectronics, consumer devices manufacturing
Common Search/ComparisonYesYes

The Flex Work From Home Dft Engineer and Flex Work From Home PCB Design Engineer roles share similarities in remote work setup and industry applications. However, DFT Engineers focus on design for testability in manufacturing, requiring specific certifications, while PCB Design Engineers concentrate on designing printed circuit boards. Both roles are essential in electronics manufacturing but differ in their core responsibilities and skill sets.

What cities are hiring for Flex Work From Home Dft Engineer jobs?

Cities with the most Flex Work From Home Dft Engineer job openings:

What are the most commonly searched types of Work From Home Dft Engineer jobs?

The most popular types of Work From Home Dft Engineer jobs are:

What states have the most Flex Work From Home Dft Engineer jobs?

States with the most job openings for Flex Work From Home Dft Engineer jobs include:

Flex Work From Home Dft Engineer jobs near you
Infographic showing various Flex Work From Home Dft Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 81% Full Time, 15% Part Time, and 3% Contract. Highlights an 87% Physical, 2% Hybrid, and 11% Remote job distribution, with an average salary of $137,309 per year, or $66 per hour.

DFT Engineer

Plano, TX • Remote

Purple Hires Inc
See more jobs at Purple Hires Incexternal

Contractor

Re-posted 26 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
 
Year of Exp: 8+ yrs to 15 yrs.
 
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.