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Role Overview

Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater - and neither has the opportunity to shape what comes next.

The AI Platform Solutions Group is seeking a Distinguished Engineer to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers.

This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware, system performance, and rack-level orchestration - directly enabling hyperscale AI training and inference workloads. You will partner with silicon vendors, hyperscalers, OEMs, and ODMs while influencing industry standards and mentoring the next generation of platform architects. If you want to architect the future of AI infrastructure at a company that is defining the connectivity backbone of modern data centers, this is your role.

Key Responsibilities

• AI Platform & Rack-Scale Architecture
• Define the end-to-end architecture for AI platforms, from node-level design to rack-scale composable systems
• Drive adoption of PCIe-based fabrics for disaggregated compute, memory, and accelerator scalability
• Architect solutions for GPU/accelerator-dense systems optimized for AI training and inference workloads
• Lead integration of connectivity solutions - retimers, switches, and fabric controllers - aligned with Astera Labs' product ecosystem

• Firmware & Platform Leadership
• Drive innovation in server BIOS/UEFI architecture, OpenBMC-based platform management, Redfish APIs for scalable infrastructure control, and lifecycle provisioning frameworks
• Lead system bring-up and ensure seamless firmware-hardware-software integration across complex AI platforms
• Define the technical vision and multi-year firmware roadmap for AI infrastructure platforms

• Performance & Optimization
• Own end-to-end AI platform performance strategy including PCIe topology optimization, bandwidth scaling, latency reduction, and CPU performance tuning for AI orchestration workloads
• Drive memory performance optimization across DDR, NUMA, and emerging memory expansion technologies
• Lead performance tuning for multi-accelerator systems (GPU/ASIC/FPGA), high-throughput data pipelines, and distributed AI workloads

• Ecosystem & Industry Leadership
• Collaborate with silicon vendors (CPU, GPU, AI accelerators), connectivity ecosystem partners, OEMs, ODMs, and hyperscalers
• Influence industry standards across OpenBMC, Redfish, OCP, and related consortia
• Mentor senior engineers and grow deep technical bench strength across the organization
• Represent Astera Labs as a recognized thought leader in AI infrastructure and platform innovation

Basic Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field
• 15+ years of experience in system architecture, server firmware, or platform engineering
• Deep expertise in server BIOS/UEFI, OpenBMC and BMC firmware stacks, and Redfish or datacenter management frameworks
• Strong knowledge of PCIe architecture and performance optimization (Gen4/5/6)
• Experience with CPU, memory, and system-level performance tuning for high-performance computing or AI platforms
• Strong programming experience in C/C++ and low-level system software
• Proven track record of leading cross-functional, large-scale architecture initiatives

Preferred Qualifications

• Master's degree or PhD in Computer Science, Electrical Engineering, or a related field
• Experience with rack-scale composable infrastructure and disaggregated architectures
• Background in AI training clusters, accelerator-based systems, or hyperscale datacenter design
• Expertise in high-speed interconnect solutions such as retimers, switches, and fabric ICs
• Experience with platform lifecycle management systems and fleet-level automation
• Contributions to industry standards bodies or open-source firmware ecosystems
• Demonstrated ability to define multi-year technical roadmaps and influence executive strategy