2

Entry Level Memory Design Engineer Jobs in Austin, TX

Design Verification Engineer - Internal IP

Austin, TX · On-site

$120 - $160/hr

  • Medical

  • Dental

  • Vision

Job Summary We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ... Hands‑on experience verifying datapaths, memory systems, interconnects, or high-throughput ...

ASIC Engineer, Annapurna Labs

Austin, TX · On-site

$164K/yr

We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures ... as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level ...

ASIC Engineer, Annapurna Labs

Austin, TX · On-site

$164K/yr

We're looking for an ASIC Design Engineer to help us trail-blaze new technologies and architectures ... as interconnects, DMAs, Memory sub-systems, accelerator engines, debug and system level ...

Analog Designer 4

Austin, TX · On-site

$70 - $74/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

SERDES or memory PHY design experience. * Understanding of power noise generation and sensitivity ... Bachelors or Masters degree in Electrical or Computer Engineering. Benefits Our Benefits Include:

Formal Verification Engineer

Austin, TX · On-site

$134K/yr

As part of our Silicon Technologies group, you'll help design and manufacture our next-generation ... Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power ...

Roadway Project Engineer (Entry Level)

Round Rock, TX · On-site

$62K - $82K/yr

Garver is seeking an entry-level Roadway Project Engineer to join our growing Transportation Team ... Different roadway design components include typical sections, geometric layouts, drainage and ...

Showing results 41-60

Entry Level Memory Design Engineer information

See Austin, TX salary details

$29.7K

$68.8K

$117K

How much do entry level memory design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for entry level memory design engineer in Austin, TX is $68,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $51,000.00 and $77,800.00 per year, depending on experience, location, and employer.

What is an entry level memory design engineer?

Entry Level Memory Design Engineers are professionals who assist in designing, developing, and testing memory components such as SRAM, DRAM, and flash memory used in electronic devices. They typically work as part of a larger engineering team, focusing on circuit design, simulations, and verification tasks. These roles are ideal for recent graduates in electrical or computer engineering who are interested in semiconductor technology and low-level hardware design. Entry level engineers receive mentorship from senior engineers and gain hands-on experience with industry-standard design tools and processes.

What are the typical responsibilities of an entry level memory design engineer during a project cycle?

As an Entry Level Memory Design Engineer, you will typically be involved in tasks such as designing memory circuits, running simulations to verify circuit performance, and assisting with layout planning. You will often work closely with senior engineers to debug and optimize designs, as well as collaborate with verification and testing teams to ensure products meet specifications. Throughout a project cycle, you may also help document design processes and contribute to design reviews, gaining valuable exposure to the full life cycle of integrated circuit development.

What are the key skills and qualifications needed to thrive as an entry level memory design engineer, and why are they important?

To thrive as an Entry Level Memory Design Engineer, you need a solid background in electrical engineering or a related field, with strong knowledge of digital and analog circuit design fundamentals. Familiarity with industry-standard EDA tools like Cadence or Synopsys, as well as basic programming skills in languages such as Verilog or VHDL, is typically required. Attention to detail, problem-solving ability, and effective teamwork are crucial soft skills for this role. These skills ensure precise and innovative memory circuit designs that meet performance, power, and reliability requirements in semiconductor products.

What are the most commonly searched types of Memory Design Engineer jobs in Austin, TX?

The most popular types of Memory Design Engineer jobs in Austin, TX are:

Infographic showing various Entry Level Memory Design Engineer job openings in Austin, TX as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 9% Part Time, and 5% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $68,752 per year, or $33.1 per hour.

Software R&D Engineer, VLSI Physical Design - New College Grad 2026

Nvidia

Austin, TX • Hybrid

$134K - $138K/yr

Full-time

Re-posted 5 days ago


Nvidia rating

9.6

Company rating: 9.6 out of 10

Based on 17 frontline employees who took The Breakroom Quiz

7th of 245 rated software companies


Job description

NVIDIA's success builds on a foundation of industry leading hardware. We achieve distinction through extensive design optimization, including combining the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and specialized algorithms for VLSI design. We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.). Understanding both software and hardware aspects is the key. Creativity and self-drive to explore and perfect fast, high-capacity software is required. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, it does not get any better than this!

Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We're not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles.

What you'll be doing:

  • Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.

  • Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.

  • We as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:

  • Masters or PhD in Electrical Engineer or Computer Science (or equivalent experience).

  • Experience with VLSI algorithms development using C++.

  • Understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.

  • Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC and typical design flows written in Perl, Tcl, and Python.

Ways to stand out from the crowd:

  • C++14 or newer experience, such as lambdas and concurrency.

  • Understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA.

  • Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.

  • Highly driven to craft software towards improving PPA with a dedication to continuous improvement.

  • Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design.

NVIDIA is widely considered to be one of the technology world's most desirable employers, and due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until July 26, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

What Nvidia employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


Nvidia logo

About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993