As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Develop distributed simulation clusters to accelerate circuit verification at scale * Manage and ...
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Develop distributed simulation clusters to accelerate circuit verification at scale * Manage and ...
FPGA Engineer II with Security Clearance
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA Engineer II with Security Clearance
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
ASIC & FPGA Design Engineer Stf
Orlando, FL · On-site +1
$114K - $158K/yr
Drive DRC, LVS and ERC verification to achieve full closure for each target process. Perform or ... Manage tape out sign off packages, including documentation, design rule decks and release notes.
ASIC & FPGA Design Engineer Stf
Orlando, FL · On-site +1
$114K - $158K/yr
Drive DRC, LVS and ERC verification to achieve full closure for each target process. Perform or ... Manage tape out sign off packages, including documentation, design rule decks and release notes.
ASIC & FPGA Design Engineer Stf
Orlando, FL · On-site +1
$114K - $158K/yr
Drive DRC, LVS and ERC verification to achieve full closure for each target process. Perform or ... Manage tape out sign off packages, including documentation, design rule decks and release notes.
ASIC & FPGA Design Engineer Stf
Orlando, FL · On-site +1
$114K - $158K/yr
Drive DRC, LVS and ERC verification to achieve full closure for each target process. Perform or ... Manage tape out sign off packages, including documentation, design rule decks and release notes.
FPGA ENGINEER II with Security Clearance
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA ENGINEER II with Security Clearance
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA ENGINEER II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA ENGINEER II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA Engineer II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA Engineer II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA Engineer II
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA Engineer II
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA ENGINEER II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA ENGINEER II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA Engineer II
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA Engineer II
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA ENGINEER II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
FPGA ENGINEER II
Mckinney, TX · On-site
$120K - $155K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding ... Experience with source code management, design reviews, and code release in a team development ...
ASIC Design Engineer
Beaverton, OR · On-site
... of the SOC Design, SOC Design- Verification, Emulation, STA, and Physical Design teams ... clock management designs desirable.Ability to communicate optimally across all internal ...
ASIC Design Engineer
Beaverton, OR · On-site
... of the SOC Design, SOC Design- Verification, Emulation, STA, and Physical Design teams ... clock management designs desirable.Ability to communicate optimally across all internal ...
... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ... management designs desirable. Ability to communicate optimally across all internal groups ...
... Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems ... management designs desirable. Ability to communicate optimally across all internal groups ...
ASIC Engineer 4
$195K - $247K/yr
... manage the layout process including floor-planning, placement, routing, physical verification, and ... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. ...
ASIC Engineer 4
$195K - $247K/yr
... manage the layout process including floor-planning, placement, routing, physical verification, and ... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. ...
ASIC Engineer 4
Minneapolis, MN · On-site
$195K - $247K/yr
... manage the layout process including floor-planning, placement, routing, physical verification, and ... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. ...
ASIC Engineer 4
Minneapolis, MN · On-site
$195K - $247K/yr
... manage the layout process including floor-planning, placement, routing, physical verification, and ... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. ...
SoC Digital Verification Engineer, Multimedia Lab
San Jose, CA · On-site
$156K - $316K/yr
... and ASIC) from the ground up to better serve billions of users. We are looking for strong video ... managing confidential information including proprietary and trade secret information and access to ...
SoC Digital Verification Engineer, Multimedia Lab
San Jose, CA · On-site
$156K - $316K/yr
... and ASIC) from the ground up to better serve billions of users. We are looking for strong video ... managing confidential information including proprietary and trade secret information and access to ...
ASIC & FPGA Design Engineer Sr
Orlando, FL · On-site
$114K - $158K/yr
You will integrate hardware, develop test plans and verify performance on demanding space based ... Experience managing configuration control (GitLab preferred). * Experience with Vivado and Vitis ...
ASIC & FPGA Design Engineer Sr
Orlando, FL · On-site
$114K - $158K/yr
You will integrate hardware, develop test plans and verify performance on demanding space based ... Experience managing configuration control (GitLab preferred). * Experience with Vivado and Vitis ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$123K - $216K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Develop distributed simulation clusters to accelerate circuit verification at scale * Manage and ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$123K - $216K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Develop distributed simulation clusters to accelerate circuit verification at scale * Manage and ...
... verification using test benches constructed using UVM, System C and DPI-C. • Learn about ... manage stress and work safely and respectfully with others, exhibit trustworthiness and ...
... verification using test benches constructed using UVM, System C and DPI-C. • Learn about ... manage stress and work safely and respectfully with others, exhibit trustworthiness and ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$123K - $216K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Develop distributed simulation clusters to accelerate circuit verification at scale * Manage and ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$123K - $216K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Develop distributed simulation clusters to accelerate circuit verification at scale * Manage and ...
Entry Level Asic Verification Manager information
Job description
Team Description:
The Infrastructure Team builds the foundation that enables the company to operate safely, robustly, and move at light-speed. We run a mixture of cloud-based and on-prem systems and have a user base spanning from highly technically proficient engineers to non-technical scientists and doctors; but all of them need solid systems, rugged networking, and bullet-proof software to do their jobs.
Job Responsibilities and Description:
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span all layers of the work environment stack, from deployment of physical hardware on the manufacturing line, to custom tooling to stream neural recordings from implants. You will:
- Build and maintain scalable EDA compute infrastructure for analog and digital chip design
- Develop distributed simulation clusters to accelerate circuit verification at scale
- Manage and optimize license infrastructure across multiple EDA vendors
- Architect high-performance and robust shared storage for terabyte-scale design data
- Develop build-system infrastructure and tooling for firmware targeting custom ASICs
- Automate bare-metal server provisioning and lifecycle management for EDA compute fleets
- Enhance developer experience for IC design and firmware engineers through monitoring, self-service tooling, and robust automation
Tech Stack:
- Rust, Python, Go
- Cadence Virtuoso, Cadence Spectre
- Terraform, Ansible, Packer, MAAS
- Bazel and Nix
- Prometheus, ClickHouse, Grafana
- Ray, Docker, Kubernetes
- AWS, OCI (Oracle Cloud Infrastructure)
- RHEL, Ubuntu
Required Qualifications:
- Experience administering EDA compute environments and toolchains (Cadence, Synopsys, Siemens/Mentor)
- Working knowledge of FlexLM license server administration and capacity management.
- Working knowledge of compiled languages, ideally Rust, Go, or C/C++.
- Experience with high-performance Linux storage: NFS, ZFS, Ceph, iSCSI, or similar.
- Systems administration experience on RHEL and Ubuntu, kernel tuning for compute workloads
- Familiarity with distributed compute frameworks (Ray, Slurm, LSF, or similar)
- Experience with bare-metal provisioning and lifecycle management at datacenter scale
- Familiarity with embedded cross-compilation toolchains and build systems (ARM, Bazel, Nix)
- Experience with multi-cloud deployments and hybrid on-prem/cloud architectures
- Bachelor's degree in computer science, a related field, or an equivalent combination of education, training, and/or experience
About NEURALINK
Sourced by ZipRecruiter
Industry
Biotechnology research and development
Company size
201 - 500 Employees
Headquarters location
San Francisco, CA, US
Year founded
2016