ZipRecruiter

Log In

2

Entry Level Asic Design Engineer Jobs in Bothell, WA

Amazon

Sr. FPGA Engineer, Amazon Leo

Redmond, WA · On-site

$145.60K - $187K/yr

... ASIC designs for advanced satellite communication systems. Position Overview: We are seeking an experienced Senior FPGA Engineer to join our LEO silicon team. This role will contribute to the design ...

Amazon

Sr. FPGA Engineer, Amazon Leo

Redmond, WA

$145.60K - $187K/yr

... ASIC designs for advanced satellite communication systems. Position Overview: We are seeking an experienced Senior FPGA Engineer to join our LEO silicon team. This role will contribute to the design ...

legence

Mechanical Design Engineer

Renton, WA

$85.50K - $115.90K/yr

Entry Level Mechanical Engineer Employment Type: Full-Time Schedule: In Office M-F Salary: $80,200 ... This individual will be working with a team to design, analyze, and coordinate the mechanical ...

legence

Mechanical Design Engineer

Renton, WA · On-site

$85.50K - $115.90K/yr

Entry Level Mechanical Engineer Employment Type: Full-Time Schedule: In Office M-F Salary: $80,200 ... This individual will be working with a team to design, analyze, and coordinate the mechanical ...

SpaceX

RFIC Design Engineer (RFIC Engineering)

Redmond, WA · On-site

$145K - $175K/yr

RFIC DESIGN ENGINEER (RFIC ENGINEERING) At SpaceX we're leveraging our experience in building ... Work with system architects, modem/DSP and ASIC engineers to partition functions between hardware ...

Legence

Mechanical Design Engineer

Renton, WA · On-site

$80.20K - $83K/yr

... Entry Level Mechanical Engineer Employment Type: Full-Time Schedule: In Office M-F Salary: $80,200 ... This individual will be working with a team to design, analyze, and coordinate the mechanical ...

Sunbelt Controls

Controls Design Engineer II

Renton, WA · On-site

Performs as a lead Design Engineer in the production of controls systems design drawings, sequence ... Participates in the ongoing development program with other entry level engineers. EDUCATION AND ...

Sunbelt Controls

Controls Design Engineer II

Renton, WA · On-site

Performs as a lead Design Engineer in the production of controls systems design drawings, sequence ... Participates in the ongoing development program with other entry level engineers. EDUCATION AND ...

next page

Showing results 1-20

People also search for

All JobsEntry Level Asic Design Engineer JobsEntry Level Asic Design Engineer Jobs in Bothell, WA

Entry Level Asic Design Engineer information

See Bothell, WA salary details

$105.1K

$167.9K

$225.8K

How much do entry level asic design engineer jobs pay per year?

As of May 30, 2026, the average yearly pay for entry level asic design engineer in Bothell, WA is $167,902.00, according to ZipRecruiter salary data. Most workers in this role earn between $147,000.00 and $201,200.00 per year, depending on experience, location, and employer.

What is an Entry Level ASIC Design Engineer job?

An Entry Level ASIC Design Engineer is responsible for assisting in the design, development, and testing of Application-Specific Integrated Circuits (ASICs). They work with senior engineers to define specifications, write hardware descriptions using languages like Verilog or VHDL, and perform simulations to validate designs. They may also collaborate with verification teams, support synthesis and timing analysis, and help troubleshoot design issues. This role requires a strong foundation in digital logic design, semiconductor fundamentals, and hardware design methodologies.

What are the key skills and qualifications needed to thrive in the Entry Level Asic Design Engineer position, and why are they important?

To thrive as an Entry Level ASIC Design Engineer, you need a solid understanding of digital logic design, hardware description languages (such as Verilog or VHDL), and a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Synopsys or Cadence and experience with simulation and verification environments are commonly expected. Strong problem-solving skills, effective communication, and the ability to work collaboratively make candidates stand out. These competencies enable precise design, successful project collaboration, and adaptation to the fast-paced, detail-oriented nature of ASIC development.

What are the typical daily responsibilities for an Entry Level ASIC Design Engineer?

As an Entry Level ASIC Design Engineer, your daily tasks often include writing and debugging code in hardware description languages, running simulations to verify functionality, and collaborating with senior engineers to implement and optimize chip designs. You may also assist with testbench development, participate in design reviews, and document your progress for project tracking. Expect to work closely with a multidisciplinary team—including verification, layout, and software engineers—to ensure the final product meets performance and reliability standards. This collaborative, fast-paced environment provides valuable hands-on experience and growth opportunities for engineers early in their careers.
More about Entry Level Asic Design Engineer jobs
What are popular job titles related to Entry Level Asic Design Engineer jobs in Bothell, WA? For Entry Level Asic Design Engineer jobs in Bothell, WA, the most frequently searched job titles are:
What job categories do people searching Entry Level Asic Design Engineer jobs in Bothell, WA look for? The top searched job categories for Entry Level Asic Design Engineer jobs in Bothell, WA are:
What cities near Bothell, WA are hiring for Entry Level Asic Design Engineer jobs? Cities near Bothell, WA with the most Entry Level Asic Design Engineer job openings:
Entry Level Asic Design Engineer jobs near you
Infographic showing various Entry Level Asic Design Engineer job openings in Bothell, WA as of May 2026, with employment types broken down into 1% Locum Tenens, and 99% Full Time. Highlights an 96% Physical, and 4% Remote job distribution, with an average salary of $167,902 per year, or $80.7 per hour.
FPGA/ASIC Design Engineer (Silicon Engineering)

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Redmond, WA • On-site

$140K - $175K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 9 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 142 frontline employees who took The Breakroom Quiz

12th of 59 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog
  • Optimize designs for power, performance and area
  • Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
  • Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
  • Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.
  • Collaborate with software engineers in developing production software for your designs

BASIC QUALIFICATIONS:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

PREFERRED SKILLS AND EXPERIENCE:
  • ASIC/FPGA system integration experience
  • Proficiency in Python, C/C++, and Bash
  • Experience in designing DSP, digital communication system datapath blocks, and/or modem design
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
  • Experience and understanding of AXI/AHB/APB protocols
  • Strong foundation in electrical engineering fundamentals
  • Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Demonstrated ability to work in a highly cross-functional role
  • Enjoys being challenged and learning new skills
  • Master's in Electrical/Computer Engineering or related field

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:
Pay range:
ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year
ASIC Design Engineer/Level II: $140,000.00 - $175,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

What SpaceX employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply