Eda Design Jobs (NOW HIRING)

There is energy here...energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

Job Description:

Description: Director - CAD Design Engineering & EDA Infrastructure

Role Overview

The Director of EDA Design Methodology & Infrastructure will lead the development, deployment, and optimization of design automation flows, tools, and infrastructure across the organization. This role ensures that engineering teams have cutting-edge, scalable, and efficient methodologies to deliver complex semiconductor designs on time and with high quality.

• EDA Strategy: Define and drive the long-term vision for EDA methodologies, flows, and infrastructure to support advanced semiconductor design.
• Methodology Development: Architect and implement design flows for RTL-to-GDSII, verification, physical design, timing closure, and sign-off.
• Infrastructure Management: Oversee compute farms, license servers, cloud integration, and tool deployment to ensure scalability and efficiency.
• GenAI Strategy for the EDA Design and Methodology
• Cross-functional Collaboration: Partner with design, verification, CAD, and IT teams to align methodologies with project needs.
• Tool Evaluation: Evaluate, benchmark, and deploy EDA tools from major vendors; negotiate with suppliers to optimize cost and performance.
• Innovation Leadership: Introduce automation, AI/ML-driven flows, and cloud-native solutions to accelerate design productivity.
• Team Leadership: Build and mentor a high-performing team of CAD/EDA engineers; foster a culture of technical excellence and innovation.
• Process Standardization: Establish best practices, documentation, and training programs for design teams worldwide.
• Risk Management: Identify and mitigate risks in tool flows, infrastructure, and project schedules.

Qualifications

• Education: Master's in electrical engineering, Computer Engineering, or related field.
• Experience: 15+ years in semiconductor design, with at least 7 years in EDA methodology leadership.
• Technical Expertise: Deep knowledge of RTL design, verification, synthesis, place & route, timing analysis, and sign-off flows.
• Infrastructure Knowledge: Strong background in compute infrastructure, cloud-based design environments, and license management.
• Leadership Skills: Proven ability to lead global teams, manage vendor relationships, and drive organizational change.
• Soft Skills: Excellent communication, negotiation, and strategic planning abilities.

This role is pivotal in enabling the company to design next-generation chips efficiently and competitively. By leading EDA methodology and infrastructure, the director ensures that engineering teams can innovate faster, reduce time-to-market, and maintain design quality at scale.

Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visitwww.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.