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Dta Engineer Jobs (NOW HIRING)

Intel

Senior EDA Tools Software Engineer

Santa Clara, CA · On-site

$143K - $189K/yr

... DTA), RAS error logic, address maps, firmware tables etc. The chassis automation tool will collect ... You will also mentor the junior engineer joining alongside you.AI-assisted workflows are part of ...

YMCA of Greater Boston

Registered Dietitian

Boston, MA · On-site

$34 - $45.75/hr

The YMCA of Greater Boston is also a partner to the Department of Transitional Assistance (DTA) and ... Implement education curriculum and programming at grocery sites, Mobile Market Food Truck locations ...

TekCommands Inc

Biztalk Admin

OR · Remote

Optimize MessageBox, DTA, and BAM databases. Manage SQL cleanup jobs, host throttling, memory usage ... Automate deployment pipelines (Azure DevOps / PowerShell / MSBuild). Manage SSO, SSL/TLS ...

SOSi

Data Scientist

Redstone Arsenal, AL · Hybrid

... programming, handling SQL databases, and working in command line interfaces. You will leverage scientific techniques to transform petabyte-scale data into insightful data products to enable dta ...

SOSi

Data Scientist

Huntsville, AL · On-site

... programming, handling SQL databases, and working in command line interfaces. You will leverage scientific techniques to transform petabyte-scale data into insightful data products to enable dta ...

JT4, LLC

Systems Administrator II

Edwards, CA · On-site

JT4, LLC provides engineering and technical support to multiple western test ranges for the U.S ... Key DTA responsibilities include processing Assured File Transfer (AFT) forms, ensuring Data at ...

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As of Sep 9, 2026, the average yearly pay for dta engineer in the United States is $107,956.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $133,500.00 per year, depending on experience, location, and employer.

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Senior EDA Tools Software Engineer

Santa Clara, CA • On-site

Intel
Manufacturing • 10K+ employees
Learn more about Intelexternal

$143K - $189K/yr

Full-time

Medical, Retirement, PTO

Re-posted 2 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 162 rated electronics manufacturers

Job description

Job Details:Job Description: 

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel,you'llhave the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.

Life at Intel

Intel is seeking aSeniorEDA SoftwareEngineer for the Silicon Chassis team. In this technical hands-on leadership role, you will help define end-to-end automation strategy and lead development of the chassis automation tool. Chassis refers to non-compute infrastructure in any soc, which provide essential platform services and typically include interconnects, protocol bridges, clock/reset/power, security, debug/trace/analytics (DTA), RAS error logic, address maps, firmware tables etc. The chassis automation tool will collect user requirements, and translate these requirements into chassis parameters, topology and generate RTL, register definitions, integration and verification collateral for the chassis using highly parameterized and configurable sub-components.
You will work directly with chassis architecture, RTL design, verification, and SOC integration teams to encode the architectural rules of the interconnect and develop a reliable, testable automation framework.You will also mentor the junior engineer joining alongside you.AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.
WhyThis Role IsExciting:

  • Build abrand newautomation platform by defining thetool, schema, andmethodologyfrom the ground up.

  • Directly influence next-generation SoC chassis architectures and delivery.

  • Collaborate across architecture, RTL, DV, and SoC integration teams.

  • Drive technical direction andestablishbest practices with broad organizational impact.

Key Responsibilities

  • Architect, design, and implement a new chassis automation tool to meet requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility.

  • Analyze chassis and interconnect architecture specifications, along with high-level SoC requirements, and build tooling and infrastructure to translate these requirements into generated outputs such as RTL, RDL, verification collateral, timing, and integration artifacts.

  • Develop automation flows that convert architectural intent into concrete implementations, including topology generation, parameter derivation, register definitions, and associated collateral.

  • Integrate with frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (e.g., RTL, Verilog, SDC, RDL), ensuring correctness and consistency.

  • Enable Power, Performance, and Area (PPA) optimization loops by building automation and analysis capabilities that evaluate design trade-offs and guide configuration decisions.

  • Work closely with architecture, RTL design, verification, and SoC integration teams to ensure the tool accurately captures requirements and produces outputs that meet downstream expectations.

  • Participate in and contribute to technical reviews with cross-functional stakeholders, incorporating feedback to improve tool capabilities, usability, and quality.

  • Drive end-to-end execution frominitialconcepts and specifications through development, deployment, and ongoing maintenance of the automation framework.

  • Lead delivery of the tool and associated outputs to multiple internal customers, balancing competing requirements, schedules, and priorities whilemaintaininghigh quality.

  • Collaborate across organizational boundaries and contribute beyond immediate role scope when needed to unblock execution and ensure overall program success.

  • Mentor and guide engineers, helpingestablishbest practices in software design, testing, and maintainability, and elevating overall team effectiveness.

The ideal candidate willpossessthe following behavioral traits:

  • Ability to interpret architecture or micro-architecture specifications and translate them into robust software implementations.

  • Excellent communication, problem-solving, and organizational skills, witha track recordof delivering high-quality solutions on schedule.

Qualifications:

Minimum qualifications arerequiredto be initially considered for this position. Preferred qualifications are in addition to theminimumrequirements and are considered a plus factor inidentifyingtop candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internshipexperiencesand orschoolwork/classes/research.
Minimum Qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, or a related field, with 7+ years of experience in CAD/EDA tooling, design automation, or semiconductor development ORMaster's degree in Electrical Engineering, Computer Science, or a related field, with 6+ years of experience in CAD/EDA tooling, design automation, or semiconductor.

  • 5+ years' experience of building scalable, maintainable software systems and frameworks rather than one-off scripts.

  • 4+ years' experience in Python or similar languagedesigning andvalidatingstructured schemas using formats such as JSON or YAML.

  • 2+year's experiencetemplating systems or code generation frameworks used for structured RTL or collateral generation.

  • 1+year experiencewithversioncontrol (Git), code reviews, unit/integration testing, and CI/CD practices.

Preferred Qualifications:

  • Experience building and developing EDA tooling

  • 2+ years' experience with digital SoC design concepts, including RTL hierarchy, synthesis flows, and parameterized IP design.

  • 2+ years' experience with System Verilog to understand andvalidategenerated design outputs.

  • Experience with Network-on-Chip (NoC) architectures or high-performance interconnect protocols such as AXI, CHI, PCIe, UCIe, or similar.
    Familiarity with IP packaging, configuration, and integration methodologies, including standards such as IP-XACT.

  • Exposuretoindustry EDA tools and design flows.

  • Knowledge of graph-basedalgorithms (e.g.NetworksX)anddatastructures relevant to topology generation, connectivity modeling, or routing problems.

  • Prior experience working in a semiconductor product development environment, such as CAD, RTL design, or verification.

  • Experience in GUI development


Requirements listed would be obtained through a combination of industry relevant job experience, internshipexperiencesandorschoolwork/classes/research.

Benefits at Intel

Our total rewards package goesabove and beyondjust a paycheck. Whetheryou'relooking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go toIntel Benefits | Intel Careersfor details of benefits available to you. Intel reserves the right to modify, change ordiscontinuebenefit plans at any time in its sole discretion.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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