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Drc Lvs Verification Jobs (NOW HIRING)

OMNIVISION

Sr. EDA Flow Engineer

Santa Clara, CA · On-site

$110K - $145K/yr

Identify and prioritize high-impact opportunities to apply AI/ML to chip design and verification ... DRC/LVS, ECO optimization, and debug acceleration * Integrate AI solutions into existing CAD ...

Intel

Physical Verification Engineer

Phoenix, AZ · On-site

$135K/yr

Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations * Drive methodology improvements to streamline customer design workflows and enhance ...

Astera Labs

Physical Design/CAD Engineer

San Jose, CA

$160K - $195K/yr

Opportunity to own a small block partition and closure (PnR, STA, DRC and LVS etc) based on interest and capacity * Partner closely with design, implementation, and verification teams to drive block ...

Intel

Physical Verification Engineer

Santa Clara, CA · On-site

$159K/yr

Provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations * Drive methodology improvements to streamline customer design workflows and enhance ...

Analogdevices

Staff PDK Engineer

Beaverton, OR

Develop as well as improve physical verification (DRC/LVS) rule decks. * Develop rule decks for verifying Electrical Rule Checks (ERC). * Develop and validate Parasitic Extraction (PEX) technology ...

Analogdevices

Staff PDK Engineer

Dallas, TX

Develop as well as improve physical verification (DRC/LVS) rule decks. * Develop rule decks for verifying Electrical Rule Checks (ERC). * Develop and validate Parasitic Extraction (PEX) technology ...

Analogdevices

Staff PDK Engineer

Wilmington, MA

Develop as well as improve physical verification (DRC/LVS) rule decks. * Develop rule decks for verifying Electrical Rule Checks (ERC). * Develop and validate Parasitic Extraction (PEX) technology ...

Analogdevices

Staff PDK Engineer

Durham, NC

Develop as well as improve physical verification (DRC/LVS) rule decks. * Develop rule decks for verifying Electrical Rule Checks (ERC). * Develop and validate Parasitic Extraction (PEX) technology ...

Analog Devices

Staff PDK Engineer

Beaverton, OR · On-site

Develop as well as improve physical verification (DRC/LVS) rule decks. * Develop rule decks for verifying Electrical Rule Checks (ERC). * Develop and validate Parasitic Extraction (PEX) technology ...

Nvidia Corporation

Senior Calibre CAD Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

You would be responsible for supporting and maintaining CAD tools used by IC designers including Virtuoso, IC-Manage, DRC/LVS verification tools, extractions, and spice simulation tools. * Work with ...

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Drc Lvs Verification information

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$31

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How much do drc lvs verification jobs pay per hour?

As of Jun 10, 2026, the average hourly pay for drc lvs verification in the United States is $31.05, according to ZipRecruiter salary data. Most workers in this role earn between $24.28 and $35.10 per hour, depending on experience, location, and employer.

What is the difference between Drc Lvs Verification vs Drc Lvs Testing?

AspectDrc Lvs VerificationDrc Lvs Testing
Primary FocusEnsuring design correctness and compliance with specificationsExecuting tests to validate functionality and performance
Work EnvironmentDesign teams, verification labs, simulation environmentsTest benches, hardware labs, validation setups
Required SkillsHardware description languages, verification methodologies, scriptingTesting tools, debugging, hardware/software integration

While Drc Lvs Verification focuses on verifying the correctness of the design through simulation and formal methods, Drc Lvs Testing involves executing tests on hardware or prototypes to validate real-world performance. Both roles require similar technical skills but differ in their approach and environment.

What are DRC LVS Verification engineers and what do they do?

DRC LVS Verification engineers are professionals in the semiconductor industry who ensure that integrated circuit (IC) designs are manufacturable and functionally correct. DRC stands for Design Rule Checking, which verifies that physical layouts comply with manufacturing constraints, while LVS stands for Layout Versus Schematic, which checks that the physical layout matches the intended circuit design. These engineers use specialized Electronic Design Automation (EDA) tools to identify and resolve errors before fabrication, helping to reduce costly mistakes and silicon re-spins. Their work is crucial in delivering reliable and high-yield semiconductor products.

What are some common challenges faced by DRC LVS Verification engineers, and how are they typically addressed within a team?

DRC (Design Rule Check) LVS (Layout Versus Schematic) Verification engineers often face challenges such as managing complex design databases, handling large-scale data, and resolving discrepancies between layout and schematic. To address these, teams usually adopt systematic debugging processes, utilize automation scripts, and collaborate closely with designers to quickly identify and correct errors. Regular team meetings and knowledge-sharing sessions are also common, helping engineers stay updated on evolving design rules and verification methodologies.

What are the key skills and qualifications needed to thrive as a DRC LVS Verification Engineer, and why are they important?

To thrive as a DRC LVS Verification Engineer, you need a solid understanding of semiconductor design, physical verification concepts, and a relevant engineering degree. Proficiency with EDA tools such as Calibre or Mentor Graphics for Design Rule Checking (DRC) and Layout Versus Schematic (LVS) verification is essential. Strong problem-solving skills, attention to detail, and effective communication distinguish top performers in this role. These skills ensure the accuracy and manufacturability of chip designs, preventing costly errors in the semiconductor fabrication process.
Infographic showing various Drc Lvs Verification job openings in the United States as of June 2026, with employment types broken down into 97% Full Time, and 3% Contract. Highlights an 93% Physical, 4% Hybrid, and 3% Remote job distribution, with an average salary of $64,585 per year, or $31.1 per hour.
Sr. EDA Flow Engineer

Sr. EDA Flow Engineer

OMNIVISION

Santa Clara, CA • On-site

$110K - $145K/yr

Full-time

Posted 7 days ago

Job description

Description
Position Overview:
Work closely with design teams and CAD/EDA stakeholders to identify workflow bottlenecks across the chip development lifecycle-such as DRC/CDC/STA debug, regression triage, PPA convergence, and ECO iteration. This role focuses on building scalable data pipelines and models, and integrating AI-driven solutions into production CAD and verification flows.
Responsibilities:
  • Identify and prioritize high-impact opportunities to apply AI/ML to chip design and verification workflows, spanning RTL-to-GDS, signoff, debug, and regression
  • Build and maintain data pipelines to extract, normalize, and analyze signals from EDA tool logs, reports, run artifacts, and design metadata (e.g., timing reports, violations, coverage, failures)
  • Develop ML models, heuristics, and analytics to improve efficiency and quality in areas such as STA, DRC/LVS, ECO optimization, and debug acceleration
  • Integrate AI solutions into existing CAD infrastructure, including automation systems, regression frameworks, job schedulers, and design databases
  • Collaborate with EDA vendors as needed for tool enablement, feature requests, debugging, and evaluation of vendor solutions versus internal implementations

Requirements:
  • BS or MS in Electrical Engineering, Computer Science, or equivalent industry experience
  • 2+ years of experience in CAD/EDA flow engineering, design automation, or a related semiconductor workflow role
  • Strong programming skills, with Python required; experience with shell, Tcl, or Perl as needed
  • Hands-on experience applying machine learning to real-world engineering problems
  • Solid understanding of at least one major EDA workflow domain (e.g., place & route, physical layout, DRC/LVS, STA, power, CDC, DFT, simulation/regressions)
  • Experience working with large-scale, noisy operational data (EDA logs and reports) and building robust automation around it

Annual base salary for this role in California, US is expected to be between $110,000 - $145,000. Actual pay will be determined by several factors such as relevant skills and experience, and the pay of employees in a similar role.
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