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Drc Lvs Verification Jobs (NOW HIRING)

Apple

RFIC Layout Engineer

Austin, TX · On-site

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

Apple

RFIC Layout Engineer

Austin, TX · On-site

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

Apple

RFIC Layout Engineer

Austin, TX

$115K - $203K/yr

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

Apple

RFIC Layout Engineer

Austin, TX

$163K - $290K/yr

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

Apple

RFIC Layout Engineer

Austin, TX

$115K - $203K/yr

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

Apple

RFIC Layout Engineer

Austin, TX

$115K - $203K/yr

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

Apple

RFIC Layout Engineer

Austin, TX

$163K - $290K/yr

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

Apple

RFIC Layout Engineer

Austin, TX

$163K - $290K/yr

You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design ...

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Drc Lvs Verification information

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How much do drc lvs verification jobs pay per hour?

As of Jun 10, 2026, the average hourly pay for drc lvs verification in the United States is $31.05, according to ZipRecruiter salary data. Most workers in this role earn between $24.28 and $35.10 per hour, depending on experience, location, and employer.

What is the difference between Drc Lvs Verification vs Drc Lvs Testing?

AspectDrc Lvs VerificationDrc Lvs Testing
Primary FocusEnsuring design correctness and compliance with specificationsExecuting tests to validate functionality and performance
Work EnvironmentDesign teams, verification labs, simulation environmentsTest benches, hardware labs, validation setups
Required SkillsHardware description languages, verification methodologies, scriptingTesting tools, debugging, hardware/software integration

While Drc Lvs Verification focuses on verifying the correctness of the design through simulation and formal methods, Drc Lvs Testing involves executing tests on hardware or prototypes to validate real-world performance. Both roles require similar technical skills but differ in their approach and environment.

What are DRC LVS Verification engineers and what do they do?

DRC LVS Verification engineers are professionals in the semiconductor industry who ensure that integrated circuit (IC) designs are manufacturable and functionally correct. DRC stands for Design Rule Checking, which verifies that physical layouts comply with manufacturing constraints, while LVS stands for Layout Versus Schematic, which checks that the physical layout matches the intended circuit design. These engineers use specialized Electronic Design Automation (EDA) tools to identify and resolve errors before fabrication, helping to reduce costly mistakes and silicon re-spins. Their work is crucial in delivering reliable and high-yield semiconductor products.

What are some common challenges faced by DRC LVS Verification engineers, and how are they typically addressed within a team?

DRC (Design Rule Check) LVS (Layout Versus Schematic) Verification engineers often face challenges such as managing complex design databases, handling large-scale data, and resolving discrepancies between layout and schematic. To address these, teams usually adopt systematic debugging processes, utilize automation scripts, and collaborate closely with designers to quickly identify and correct errors. Regular team meetings and knowledge-sharing sessions are also common, helping engineers stay updated on evolving design rules and verification methodologies.

What are the key skills and qualifications needed to thrive as a DRC LVS Verification Engineer, and why are they important?

To thrive as a DRC LVS Verification Engineer, you need a solid understanding of semiconductor design, physical verification concepts, and a relevant engineering degree. Proficiency with EDA tools such as Calibre or Mentor Graphics for Design Rule Checking (DRC) and Layout Versus Schematic (LVS) verification is essential. Strong problem-solving skills, attention to detail, and effective communication distinguish top performers in this role. These skills ensure the accuracy and manufacturability of chip designs, preventing costly errors in the semiconductor fabrication process.
Infographic showing various Drc Lvs Verification job openings in the United States as of June 2026, with employment types broken down into 97% Full Time, and 3% Contract. Highlights an 93% Physical, 4% Hybrid, and 3% Remote job distribution, with an average salary of $64,585 per year, or $31.1 per hour.
Semiconductor Memory circuit layout engineer

Semiconductor Memory circuit layout engineer

TekWissen

Williston, VT

Other

Posted 9 days ago

Job description

Company Description

TekWissen provides a unique portfolio of innovative capabilities that seamlessly combines clients insights, strategy, design, software engineering, and systems integration.

www.tekwissen.com 

Job Description

The position is for 1 semiconductor memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team.
The chosen candidate should have a minimum of 5-10 years of memory industry design experience.
Job Duty 1 - Full chip integration for memory chips and Array Diagnostic Monitors (ADM's)
Job Duty 2 - Full chip DRC and LVS verification
Job Duty 3 - Definition of full chip signal routing methodology
Job Duty 4 - Definition of full chip voltage grids and power distribution
Job Duty 5 - Establishing voltage/reference decoupling cap methodologies that work with signal, power, and fill requirements
Job Duty 6 - Defining floor plans of entire chips as well as subsystems

Qualifications

Required skills:
1) Expert layout of semiconductor logic, analogy, and hierarchical systems.
2) Mastery of industry standard physical design and layout tools such as Cadence and Virtuoso.
3) Ability to run design checking software, e.g. DRC, LVS.
4) Strong verbal and written communication skills.
5) Must be able to work in close, team oriented research environment.

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About TekWissen

Sourced by ZipRecruiter

TekWissen is an emerging global human capital, recruitment and IT services organization. Operating since 2009, we draw upon more than a decade of staffing experience to deliver critical talent acquisition solutions and IT engagements for our clients. We’re founded on a culture that is passionate about delivering tailored solutions, that create lasting partnerships.

Industry

Recruiting and staffing services

Company size

501 - 1,000 Employees

Headquarters location

Ann Arbor, MI, US

Year founded

2009

Social media

Twitter

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