Bachelors or Master's degree in electrical engineering or physics or computer engineering or ... In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation ...
Bachelors or Master's degree in electrical engineering or physics or computer engineering or ... In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation ...
Memory Electrical Validation Engineer
Hillsboro, OR · On-site
$190K - $269K/yr
Bachelors or Master's degree in electrical engineering or physics or computer engineering or ... In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation ...
Memory Electrical Validation Engineer
Hillsboro, OR · On-site
$190K - $269K/yr
Bachelors or Master's degree in electrical engineering or physics or computer engineering or ... In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation ...
Bachelors or Master's degree in electrical engineering or physics or computer engineering or ... In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation ...
Bachelors or Master's degree in electrical engineering or physics or computer engineering or ... In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation ...
SoC DRAM Memory Subsystem Validation Engineering Program Manager
Austin, TX · On-site
$166K - $296K/yr
Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi ...
SoC DRAM Memory Subsystem Validation Engineering Program Manager
Austin, TX · On-site
$166K - $296K/yr
Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi ...
Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi ...
Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi ...
Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi ...
Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi ...
Minimum Qualifications BS + 10 years of relevant experience Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering. Preferred Qualifications Knowledge of ...
Minimum Qualifications BS + 10 years of relevant experience Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering. Preferred Qualifications Knowledge of ...
Hardware Validation Engineer, Systems
Santa Clara, CA · On-site
$149K - $225K/yr
... DRAM, and x86 CPUs. * Supporting reviews of hardware designs and JDM validation reports, while ... Bachelors or Masters in Electrical Engineering * 3+ years of experience * Strong candidates with ...
Hardware Validation Engineer, Systems
Santa Clara, CA · On-site
$149K - $225K/yr
... DRAM, and x86 CPUs. * Supporting reviews of hardware designs and JDM validation reports, while ... Bachelors or Masters in Electrical Engineering * 3+ years of experience * Strong candidates with ...
Prior experience as an Applications, Development, Design, or Validation Engineer, or a related technical role. * Customer support experience for DRAM products. * An avid learner who approaches ...
Prior experience as an Applications, Development, Design, or Validation Engineer, or a related technical role. * Customer support experience for DRAM products. * An avid learner who approaches ...
Prior experience as an Applications, Development, Design, or Validation Engineer, or a related technical role. * Customer support experience for DRAM products. * An avid learner who approaches ...
Quick apply
Prior experience as an Applications, Development, Design, or Validation Engineer, or a related technical role. * Customer support experience for DRAM products. * An avid learner who approaches ...
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
$209K - $303K/yr
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
$209K - $303K/yr
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
$209K - $303K/yr
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
$209K - $303K/yr
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
$209K - $303K/yr
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
$209K - $303K/yr
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Memory Validation Architect
San Jose, CA · On-site
... programmable technologies that help customers differentiate, innovate, and scale across rapidly ... Collaborate with leading DRAM vendors to ensure interoperability, qualification, and early ...
Key job responsibilities As a Validation Engineer on our Machine Learning Acceleration team, you'll ... caches, DRAM, HBM), compute pipelines, and interconnect topologies - Experience applying ...
Key job responsibilities As a Validation Engineer on our Machine Learning Acceleration team, you'll ... caches, DRAM, HBM), compute pipelines, and interconnect topologies - Experience applying ...
Our team combines cloud-scale innovation with world-class expertise across silicon engineering ... caches, DRAM, HBM), compute pipelines, and interconnect topologies - Experience applying ...
Our team combines cloud-scale innovation with world-class expertise across silicon engineering ... caches, DRAM, HBM), compute pipelines, and interconnect topologies - Experience applying ...
Key job responsibilities As a Validation Engineer on our Machine Learning Acceleration team, you'll ... caches, DRAM, HBM), compute pipelines, and interconnect topologies - Experience applying ...
Key job responsibilities As a Validation Engineer on our Machine Learning Acceleration team, you'll ... caches, DRAM, HBM), compute pipelines, and interconnect topologies - Experience applying ...
Lead Hardware Design Validation Engineer - Memory Subsystem
Santa Clara, CA · On-site
$145K - $191K/yr
Apply understanding of controller design, board design, and DRAM design to define and refine ... Masters or higher in Electrical engineering (or equivalent experience). * 10+ years of relevant ...
Lead Hardware Design Validation Engineer - Memory Subsystem
Santa Clara, CA · On-site
$145K - $191K/yr
Apply understanding of controller design, board design, and DRAM design to define and refine ... Masters or higher in Electrical engineering (or equivalent experience). * 10+ years of relevant ...
Lead Hardware Design Validation Engineer - Memory Subsystem
Santa Clara, CA · On-site
$145K - $191K/yr
Apply understanding of controller design, board design, and DRAM design to define and refine ... Masters or higher in Electrical engineering (or equivalent experience). * 10+ years of relevant ...
Lead Hardware Design Validation Engineer - Memory Subsystem
Santa Clara, CA · On-site
$145K - $191K/yr
Apply understanding of controller design, board design, and DRAM design to define and refine ... Masters or higher in Electrical engineering (or equivalent experience). * 10+ years of relevant ...
Dram Validation Engineer information
See salary details
$22.60 - $27.64
2% of jobs
$27.64 - $32.69
6% of jobs
$32.69 - $37.74
13% of jobs
$39.32 is the 25th percentile. Wages below this are outliers.
$37.74 - $42.79
13% of jobs
$42.79 - $47.84
11% of jobs
The median wage is $50.36 / hr.
$47.84 - $52.88
12% of jobs
$52.88 - $57.93
9% of jobs
$61.82 is the 75th percentile. Wages above this are outliers.
$57.93 - $62.98
13% of jobs
$62.98 - $68.03
13% of jobs
$68.03 - $73.08
6% of jobs
$73.08 - $78.13
3% of jobs
$22
$51
$78
How much do dram validation engineer jobs pay per hour?
As of Sep 11, 2026, the average hourly pay for dram validation engineer in the United States is $52.00, according to ZipRecruiter salary data. Most workers in this role earn between $39.42 and $63.22 per hour, depending on experience, location, and employer.
What cities are hiring for Dram Validation Engineer jobs?
Cities with the most Dram Validation Engineer job openings:
What states have the most Dram Validation Engineer jobs?
States with the most job openings for Dram Validation Engineer jobs include:
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For Dram Validation Engineer jobs, the most frequently searched job titles are:
Memory Electrical Validation Engineer
Hillsboro, OR • On-site
Intel Corporation
• Manufacturing • 10K+ employees10,000+ employees
Full-time
Medical, Retirement, PTO
Re-posted 29 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
Job description
Job Details:
Job Description:
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
Note:
This role requires regular onsite presence to fulfill essential job responsibilities.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications:
Preferred Experience:
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Description:
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
Note:
This role requires regular onsite presence to fulfill essential job responsibilities.
- Defines electrical validation strategy for memory IO interfaces to achieve optimized electrical performance and meet product production goals.
- Validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction.
- Defines MRC (Memory Reference Code) requirements for validation and margin optimization and analyzes, validates, debugs, and optimizes MRC steps and values to optimize margins and quality.
- Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces.
- Develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation.
- Analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure.
- Applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability.
- Performs debug to identify root causes and resolves all functional and triage failures for electrical issues.
- Tests interactions between various electrical design features using validation infrastructure.
- Applies understanding of DFT and DFM to collaborate with architecture, design, and presilicon verification teams to ensure capability to validate and test IO architecture implementations.
- Prepares validation specifications, evaluates IP, and generates test reports. Ensures products conform to standards and specifications.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications:
- Bachelors or Master's degree in electrical engineering or physics or computer engineering or another relevant field
- 5+ years of experience in Memory/DDR technology
- 5+ years of hands-on validation and debug experience at system level and memory interfaces
- 5+ years of experience with industry-standard JEDEC memory protocols and test methodologies
Preferred Experience:
- Understanding platform level signal integrity and power integrity technologies a definite asset
- Experience with validation of high-speed I/O interfaces, including understanding of Tx, Rx, PLL, DLL, Clocking, and Equalization
- Knowledge of computer architecture (CPU, DDR Memory technologies) and software/firmware architecture (bios, firmware debug experience)
- Hands-on experience of validation & debug using tools such as Oscilloscopes, Signal generators, BERT, and Logic analyzers
- Familiarity of Server/Xeon Memory RAS features
- Python scripting/programming skills
- Must be a self-starter and be able to independently drive tasks to completion
- In-depth knowledge of DRAM, Memory Controller and DDRIO/PHY architectures and design/validation concepts
- Familiarity with Memory Reference Code (MRC), DDR training algorithms
- Working knowledge of high-speed analog and digital circuits of IO
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968