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Dram Engineer Jobs in Chicago, IL (NOW HIRING)

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL

$138K/yr

D in Electrical Engineering, Computer Engineering, or related fields * 12+ years of experience in ... Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs ...

Eliyan

DV - Director of Design Verification

Mundelein, IL

$138K - $169K/yr

D in Electrical Engineering, Computer Engineering, or related fields * 15+ years of experience in ... Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect ...

All JobsDram Engineer JobsDram Engineer Jobs in Chicago, IL

Dram Engineer information

See Chicago, IL salary details

$39.1K

$93.3K

$155K

How much do dram engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for dram engineer in Chicago, IL is $93,268.00, according to ZipRecruiter salary data. Most workers in this role earn between $73,700.00 and $103,000.00 per year, depending on experience, location, and employer.

What is a DRAM engineer?

DRAM Engineers are specialized professionals who design, develop, test, and optimize Dynamic Random Access Memory (DRAM) chips used in computers and electronic devices. They work on improving memory performance, power efficiency, and reliability, often collaborating with hardware and software teams. Their responsibilities may include circuit design, validation, failure analysis, and process improvement to meet the demands of modern computing applications.

How does a DRAM engineer typically collaborate with cross-functional teams during the memory development process?

As a DRAM Engineer, you'll collaborate closely with teams including circuit design, process engineering, product testing, and firmware development. This collaboration ensures that the DRAM modules meet performance, reliability, and manufacturability standards. Regular meetings, design reviews, and troubleshooting sessions are common, requiring strong communication skills and a willingness to work through technical challenges together. Being proactive in sharing insights and addressing issues early helps streamline product development and supports successful project outcomes.

What are the key skills and qualifications needed to thrive as a DRAM engineer, and why are they important?

To thrive as a DRAM Engineer, you need a solid background in electrical engineering or a related field, with expertise in semiconductor memory design and circuit analysis. Familiarity with tools such as SPICE simulators, CAD/EDA software, and experience with DRAM testing methodologies are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are crucial soft skills for this role. These competencies are important to ensure the development of reliable, high-performance memory solutions that meet industry standards.

What is the difference between Dram Engineer vs Memory Engineer?

AspectDram EngineerMemory Engineer
CredentialsBachelor's or higher in Electrical Engineering, Computer Engineering, or related fields; certifications like IEEE are commonSimilar educational background; often holds certifications in memory design or semiconductor manufacturing
Work EnvironmentDesign labs, semiconductor fabs, R&D centersDesign labs, semiconductor manufacturing facilities, R&D centers
Industry UsageMemory chip companies, electronics manufacturersMemory chip companies, electronics manufacturers
Job FocusDesign and optimize DRAM modules, ensure performance and reliabilityDesign and develop various types of memory, including DRAM, SRAM, Flash

Both Dram Engineers and Memory Engineers work in similar environments and industries, often sharing educational backgrounds and certifications. While Dram Engineers focus specifically on DRAM technology, Memory Engineers may work on a broader range of memory types. The roles are closely related, with overlapping skills in semiconductor design and testing.

What are popular job titles related to Dram Engineer jobs in Chicago, IL?

For Dram Engineer jobs in Chicago, IL, the most frequently searched job titles are:

What job categories do people searching Dram Engineer jobs in Chicago, IL look for?

The top searched job categories for Dram Engineer jobs in Chicago, IL are:

Dram Engineer jobs near you

Digital - Principal Systems/DSP Engineer

Eliyan

Mundelein, IL • On-site

Full-time

Re-posted 26 days ago

Job description

Join the leading chiplet startup! As the Principal Systems/DSP Engineer at Eliyan, you will define and drive the DSP architecture for next-generation 224G and 448G SerDes designs powering tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will own the end-to-end system modeling, equalization algorithm development, and CDR architecture for industry-leading SerDes IPs implemented on advanced 3nm/2nm process nodes. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits
Key Responsibilities:
  • Define and architect low-power DSP architectures for 224G PAM4 and 448G SerDes designs, driving key trade-offs between power, performance, and area
  • Develop and maintain behavioral models of mixed-signal transceiver circuits using MATLAB, Simulink, C, and/or Python for system-level performance prediction and design specification
  • Develop, evaluate, and optimize equalization algorithms including FFE, DFE, CTLE, and MLSE/MLSD for 224G/448G channel loss and impairment compensation
  • Derive and specify analog front-end (AFE), DAC/ADC, and PLL performance targets from system-level BER and link budget analyses
  • Design and optimize adaptive DSP algorithms for channel compensation, including adaptation convergence strategies, calibration sequencing, and robustness across PVT corners
  • Architect and evaluate clock and data recovery (CDR) algorithms and loop dynamics, including jitter tolerance analysis, bang-bang and linear CDR trade-offs, and frequency acquisition strategies
  • Perform system-level simulations and trade-off analyses balancing power consumption (digital and analog), performance, and BER requirements
  • Collaborate closely with analog, digital RTL, and physical design teams to ensure algorithm-to-implementation fidelity and power-efficient silicon realization
  • Develop and evaluate FEC solutions including inner/outer FEC architectures, RS-FEC (KP4/KP8) integration, and concatenated coding schemes per IEEE 802.3dj and OIF CEI-224G standards
  • Drive silicon bring-up and characterization test plans, correlating pre-silicon system models with post-silicon measurements to validate DSP performance
  • Define lab validation methodologies and work with characterization teams on silicon debug, performance benchmarking, and standard compliance testing
  • Provide technical leadership to customers and partners on system-level link performance, interoperability, and algorithmic optimization
Qualification:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 10+ years of experience in DSP system architecture and algorithm development for high-speed serial communication systems, with hands-on work at 112G PAM4 or higher data rates
  • Deep expertise in digital communication and signal processing theory, including PAM4 modulation, equalization architectures, CDR loop dynamics, and statistical channel modeling
  • Expert-level proficiency in system modeling using MATLAB, Simulink, C, and/or Python with demonstrated ability to build production-quality behavioral models
  • Strong working knowledge of high-speed serial protocols and standards including Ethernet (IEEE 802.3ck/df/dj), PCIe, UCIe, and OIF CEI specifications
  • Solid understanding of mixed-signal circuit design concepts (DAC/ADC architectures, PLL phase noise, AFE linearity) and their impact on DSP algorithm performance and link budget
  • Proven ability to collaborate across analog, digital, and verification teams to translate algorithmic intent into silicon-ready implementations
  • Hands-on experience with 112G/224G SerDes products with proven tapeout or silicon characterization results
  • Detailed knowledge of OIF CEI-224G and IEEE 802.3dj standards including link budget allocation, compliance test methodologies, and FEC performance metrics
  • Experience with chiplet D2D interconnects, optical/electrical interfaces (VCSEL, EML), or DRAM/HBM PHY systems a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.