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Director Fpga Engineer Jobs in Basking Ridge, NJ

QCi

Director of Engineering

Hoboken, NJ · On-site

Director of Engineering Location: On Site - Hoboken NJ Division: Technology Department: Engineering ... Experience with multiple engineering domains (FPGA, Embedded firmware, Software& applications ...

L3HHCM20

Specialist, Electrical Engineer

Clifton, NJ

$92K - $171K/yr

Specialist, Electrical Engineering (FPGA) Job Code: 40150 Job Location: Clifton, NJ Job Schedule: 9 ... Formal FPGA verification experience, UVM, Directed Testing, Code Coverage * Experience with and ...

QCi

Director of Engineering (Hoboken)

Hoboken, NJ · On-site

Director of Engineering Location: On Site - Hoboken NJ Job Summary The Director of Engineering ... Experience with multiple engineering domains (FPGA, Embedded firmware, Software& applications ...

WisEngineering

Firmware Software Engineer

Dover, NJ · On-site

Successful candidate will be a direct (W2) employee of WisEngineering. Location: On Site Picatinny ... Experience in FPGA HDL development is a plus. * Experience reading electronic component datasheet ...

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Director Fpga Engineer information

See Basking Ridge, NJ salary details

$72.1K

$151.5K

$216.9K

How much do director fpga engineer jobs pay per year?

As of Aug 4, 2026, the average yearly pay for director fpga engineer in Basking Ridge, NJ is $151,549.00, according to ZipRecruiter salary data. Most workers in this role earn between $126,800.00 and $174,700.00 per year, depending on experience, location, and employer.

How does a Director FPGA Engineer typically collaborate with cross-functional teams during a project lifecycle?

As a Director FPGA Engineer, you will frequently work alongside hardware, software, and systems engineering teams to ensure seamless integration of FPGA solutions into larger products. Collaboration often includes participating in design reviews, aligning on project timelines, and resolving technical challenges that arise during development. Effective communication skills are essential, as you will be responsible for translating FPGA-specific requirements to other teams and ensuring that deliverables meet overall project goals. This cross-functional leadership is key to driving innovation and successful project outcomes.

What does a Director FPGA Engineer do?

A Director FPGA Engineer leads teams responsible for the design, development, and implementation of Field Programmable Gate Array (FPGA) solutions within an organization. This role involves overseeing project timelines, guiding architectural decisions, ensuring high-quality standards, and collaborating with cross-functional teams such as hardware, software, and product management. Directors also mentor engineers, drive innovation, and ensure that FPGA projects align with business goals and technical requirements.

What are the key skills and qualifications needed to thrive as a Director FPGA Engineer, and why are they important?

To thrive as a Director FPGA Engineer, you need deep expertise in FPGA design, digital logic, and embedded systems, often backed by an advanced degree in electrical engineering and significant industry experience. Familiarity with hardware description languages (VHDL/Verilog), FPGA development tools (such as Xilinx Vivado or Intel Quartus), and project management certifications is highly valuable. Leadership, strategic thinking, and strong communication skills set top performers apart in this role. These capabilities ensure effective technical guidance, innovation, and successful project delivery within complex engineering teams.

What is the difference between Director Fpga Engineer vs FPGA Engineer?

AspectDirector Fpga EngineerFPGA Engineer
CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related; often with leadership experienceBachelor's or Master's in Electrical Engineering, Computer Engineering, or related
Work EnvironmentLeadership roles overseeing teams, strategic planning, project managementDesign, develop, and test FPGA hardware and firmware
Industry UsageUsed in companies with large FPGA projects, R&D, and product developmentCommon in hardware design firms, tech companies, and embedded systems

The main difference is that a Director Fpga Engineer holds a leadership position with strategic responsibilities, while an FPGA Engineer focuses on technical design and implementation. The director oversees teams and projects, whereas the FPGA Engineer is hands-on with FPGA development.

What cities near Basking Ridge, NJ are hiring for Director Fpga Engineer jobs? Cities near Basking Ridge, NJ with the most Director Fpga Engineer job openings:
Director Fpga Engineer jobs near you
Infographic showing various Director Fpga Engineer job openings in Basking Ridge, NJ as of July 2026, with employment types broken down into 80% Full Time, and 20% Contract. Highlights an 60% In-person, 20% Hybrid, and 20% Remote job distribution, with an average salary of $151,549 per year, or $72.9 per hour.

Director of eSoftware Engineering - FPGA / Equities Low Latency Trading

JPMorgan Chase & Co.

Jersey City, NJ • On-site

$204K - $285K/yr

Full-time

Medical, Retirement

Re-posted 13 days ago

JPMorgan Chase & Co. rating

8.0

Company rating: 8.0 out of 10

Based on 492 frontline employees who took The Breakroom Quiz

72nd of 170 rated banks

Job description


If you are a software engineering leader ready to take the reins and drive impact, we've got an opportunity just for you.
As a Director of eSoftware Engineering at JPMorgan Chase within the Equities Electronic Trading team, you will set technical direction and personally contribute to the design and delivery of ultra-low latency market infrastructure used in equities electronic trading. You will build ultra-low latency pipelines spanning market data ingest, processing, and distribution as well as trading and execution workflows, with rigorous verification and production-grade operational controls. This role requires deep networking expertise (including TCP/IP), experience with Layer 1 switching and low-latency connectivity (including microwave), and the ability to take large programs from requirements through delivery, coordinating with internal compute and networking service organizations and managing outside vendors. This is a technical leadership role; will guide the team through architecture, design reviews, and execution. A core priority of this role is to advance the team's adoption of AI-assisted and spec-driven FPGA development and verification workflows, including executable specifications, automated review, and traceability from spec to silicon, with examples such as AI-assisted RTL and testbench generation to improve quality, throughput, and time-to-market.
Job responsibilities
  • Architect, implement, and optimize ultra-low latency FPGA-based pipelines for market data ingest, processing, and distribution as well as trading workflows, with a focus on determinism, measurement discipline, and production readiness.
  • Design and deliver high-performance network subsystems on FPGA, including deep TCP/IP expertise and complementary protocol support (UDP, IP, multicast, ARP), time synchronization (PTP), and loss/latency instrumentation suitable for production operations.
  • Engineer and integrate Layer 1 switching and ultra-low latency signal distribution capabilities, including deterministic path design and the physical and topology constraints typical of low-latency market access environments.
  • Partner with network engineering teams and external vendors to design, validate, and operate low-latency connectivity solutions, including microwave / wireless links, with clear operational runbooks and measurable service-level objectives.
  • Own verification strategy and execution, building robust testbenches in Python/Cocotb to achieve high functional coverage, strong regression quality, and fast debug cycles.
  • Drive timing closure and performance predictability, including floorplanning, static timing analysis, CDC/RDC correctness, power optimization, and post-route validation under realistic traffic and corner conditions.
  • Serve as technical lead for a team hardware and software engineers across the program lifecycle, taking large programs from requirements through production rollout while coordinating with internal compute and networking service organizations and managing outside vendors.
  • Lead the team's adoption and scaling of AI-assisted and spec-driven workflows for FPGA development and verification, including executable specifications, spec-to-implementation traceability, AI-assisted RTL generation and refactoring, automated code review, testbench and stimulus generation, bug triage, and performance tuning, with appropriate controls for correctness, IP protection, confidentiality, and auditability.

Required qualifications, capabilities, and skills
  • Formal training or certification on software engineering concepts and 10+ years applied experience. In addition, 5+ years of experience leading technologists to manage, anticipate and solve complex technical items within your domain of expertise and more broadly across the organization
  • Strong expertise and hands-on FPGA development experience in low-latency electronic trading and HFT systems.
  • Demonstrated expertise building ultra-low latency FPGA pipelines, including end-to-end performance measurement, deterministic design techniques, and latency/throughput trade-offs.
  • Advanced verification capability using Python and Cocotb, including functional coverage, constrained/random strategies as appropriate, regression automation, and debug discipline; familiarity with SystemVerilog and UVM as complementary verification approaches.
  • Strong market data domain knowledge across ingest, processing, and distribution in production trading environments.
  • Deep understanding of networking with proven implementation and troubleshooting experience in TCP, and strong competence across UDP, IP, multicast, ARP, and PTP, including packet parsing, buffering, congestion/flow considerations, and timestamping.
  • Experience with Layer 1 switching and ultra-low latency signal distribution concepts, including deterministic path design and the physical and topology constraints typical of low-latency market access environments.
  • Hands-on experience with microwave / wireless low-latency connectivity for market access, including latency budgeting, availability and environmental considerations, link engineering trade-offs, integration with FPGA-based termination/processing, and direct collaboration with specialist vendors and carriers.

Preferred qualifications, capabilities, and skills
  • Expertise with leading FPGA vendor toolchains and devices, including high-speed transceivers and high-speed Ethernet MAC/PCS integration.
  • Host/FPGA integration experience, including PCIe, DMA, AXI, driver/firmware interfaces, and performance profiling across the full stack.
  • Familiarity with exchange connectivity protocols, including production considerations for resiliency and change management.
  • Experience with, or strong interest in, AI-assisted and spec-driven approaches to FPGA development and verification, including executable specifications, AI-assisted RTL generation and refactoring, testbench and stimulus generation, automated code review, bug triage, and performance tuning, applied with appropriate guardrails for correctness, IP protection, confidentiality, and reproducibility. The successful candidate will help build and scale this capability within the team over time; deep prior expertise is not required at hire.

About Us
JPMorganChase, one of the oldest financial institutions, offers innovative financial solutions to millions of consumers, small businesses and many of the world's most prominent corporate, institutional and government clients under the J.P. Morgan and Chase brands. Our history spans over 200 years and today we are a leader in investment banking, consumer and small business banking, commercial banking, financial transaction processing and asset management.
We offer a competitive total rewards package including base salary determined based on the role, experience, skill set and location. Those in eligible roles may receive commission-based pay and/or discretionary incentive compensation, paid in the form of cash and/or forfeitable equity, awarded in recognition of individual achievements and contributions. We also offer a range of benefits and programs to meet employee needs, based on eligibility. These benefits include comprehensive health care coverage, on-site health and wellness centers, a retirement savings plan, backup childcare, tuition reimbursement, mental health support, financial coaching and more. Additional details about total compensation and benefits will be provided during the hiring process.
We recognize that our people are our strength and the diverse talents they bring to our global workforce are directly linked to our success. We are an equal opportunity employer and place a high value on diversity and inclusion at our company. We do not discriminate on the basis of any protected attribute, including race, religion, color, national origin, gender, sexual orientation, gender identity, gender expression, age, marital or veteran status, pregnancy or disability, or any other basis protected under applicable law. We also make reasonable accommodations for applicants' and employees' religious practices and beliefs, as well as mental health or physical disability needs. Visit our FAQs for more information about requesting an accommodation.
JPMorgan Chase & Co. is an Equal Opportunity Employer, including Disability/Veterans
About the Team
J.P. Morgan's Commercial & Investment Bank is a global leader across banking, markets, securities services and payments. Corporations, governments and institutions throughout the world entrust us with their business in more than 100 countries. The Commercial & Investment Bank provides strategic advice, raises capital, manages risk and extends liquidity in markets around the world.

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