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Dfx Design Engineer Jobs (NOW HIRING)

VGAI Solutions Inc

RTL Verification Engineer

Santa Clara, CA · On-site

$158K - $193K/yr

We are looking for an experienced RTL Verification Engineer with strong expertise in DFX (Design for X), VISA/Debug, JTAG, and ASIC/SoC verification . The ideal candidate will have hands-on ...

Fortive

DFX & Engineering Manager

Everett, WA · On-site

Own the design-for-excellence agenda - manufacturability, testability, yield, and cost - across new-product introduction and end-of-life. * Own the engineering KPI bowler - first-pass yield, DPPM ...

ACE Thermal Systems

Design Engineer 2

Seminole, OK · On-site

Support DFX (Design to Cost, Manufacturability, Reliability, etc.) efforts. * Prepares Development ... S. Degree in Mechanical Engineering, Aerospace Engineering, or related field required. * 2 - 4 ...

Tektronix

DFX & Engineering Manager

Everett, WA · On-site

Own the design-for-excellence agenda - manufacturability, testability, yield, and cost - across new-product introduction and end-of-life. Own the engineering KPI bowler - first-pass yield, DPPM, and ...

ACE Thermal Systems

Design Engineer 2

Seminole, OK · On-site

Support DFX (Design to Cost, Manufacturability, Reliability, etc.) efforts. * Prepares Development ... S. Degree in Mechanical Engineering, Aerospace Engineering, or related field required. * 2 - 4 ...

Fortive

DFX & Engineering Manager

Everett, WA · On-site

Own the design-for-excellence agenda - manufacturability, testability, yield, and cost - across new-product introduction and end-of-life. * Own the engineering KPI bowler - first-pass yield, DPPM ...

Ralliant

Project Design Engineer

Boxborough, MA · On-site

This role applies DFx principles while maintaining alignment of product data across CAD, ERP, PIM, and web platforms. The position executes engineering workstreams including engineering change (ECR ...

Ralliant

Project Design Engineer

Boxborough, MA · On-site

This role applies DFx principles while maintaining alignment of product data across CAD, ERP, PIM, and web platforms. The position executes engineering workstreams including engineering change (ECR ...

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Dfx Design Engineer information

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How much do dfx design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for dfx design engineer in the United States is $93,690.00, according to ZipRecruiter salary data. Most workers in this role earn between $69,000.00 and $112,500.00 per year, depending on experience, location, and employer.

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Infographic showing various Dfx Design Engineer job openings in the United States as of August 2026, with employment types broken down into 90% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution, with an average salary of $93,690 per year, or $45 per hour.

RTL Verification Engineer

Santa Clara, CA • On-site

VGAI Solutions Inc
See more jobs at VGAI Solutions Incexternal

$158K - $193K/yr

Other

Posted 9 days ago

Job description

We are looking for an experienced RTL Verification Engineer with strong expertise in DFX (Design for X), VISA/Debug, JTAG, and ASIC/SoC verification. The ideal candidate will have hands-on experience developing and executing verification environments for debug logic, DFX features, scan/debug interfaces, and related RTL.

DFX – RTL Verification Engineer | VISA / JTAG / Debug Validation

Location: Santa Clara, CA
Duration: 12 Months

Key Responsibilities & Requirements

  • 6 – 8  years of hands-on experience in RTL Design Verification, DFX Verification, or ASIC/SoC Verification.
  • Strong experience in DFX (Design for X) verification and validation of DFX-related RTL.
  • Hands-on experience with JTAG / IEEE 1149.x architecture, TAP controllers, and boundary-scan concepts.
  • Strong knowledge of VISA (Vendor Independent Silicon Architecture) / VISA Debug and related validation methodologies.
  • Experience validating debug logic, debug access mechanisms, scan/debug interfaces, and associated RTL.
  • Strong hands-on expertise in SystemVerilog and UVM.
  • Experience developing and maintaining UVM testbenches, test scenarios, assertions, functional coverage, and verification plans.
  • Hands-on experience with simulation, waveform/debug analysis, failure investigation, and root-cause analysis.
  • Experience working within complex ASIC/SoC verification environments.
  • Good understanding of DFT/DFX concepts, scan architectures, TAP controllers, JTAG, and boundary scan.
  • Strong scripting/programming skills using Python, Perl, Tcl, or similar languages.
  • Experience with industry-standard verification and debug tools such as Synopsys VCS/Verdi, Siemens Questa/ModelSim, or equivalent is preferred.

 

Ideal Candidate

The ideal candidate should be able to independently drive DFX/VISA/JTAG verification activities, develop robust SystemVerilog/UVM-based verification environments, debug complex RTL failures, and work closely with Design, DFT, Architecture, and Silicon Validation teams.

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