1

Design Verification Engineer Jobs in Pennsylvania

... Verification Plan and Report (DVP&R) to verify your design intent. • Support the Project Engineers with effective design plans for New Product Introductions (NPI) or Life Cycle Management (LCM ...

Product Design Engineer

Fairview, PA · On-site

$115K - $138K/yr

Lead engineering activities throughout the product development lifecycle, including concept ... Perform electrical analysis, circuit simulation, and design verification using PSpice, ETAP, or ...

Product Design Engineer

Fairview, PA

$115K - $138K/yr

Lead engineering activities throughout the product development lifecycle, including concept ... Perform electrical analysis, circuit simulation, and design verification using PSpice, ETAP, or ...

Evaluates and verifies optical designs from concept to mass production to meet requirements for ... Designs or guides mechanical engineers in the design of mechanical assemblies of optical elements ...

Summary As a member of Microchip's engineering community, your primary responsibility will be to design, simulate, and verify various RTL-based blocks on our devices. Microchip's designs are an SOC ...

Mechanical Design Engineer

Yocumtown, PA · On-site

$72K - $98K/yr

We are currently seeking a mechanical design engineer to join our High Speed IO Connector ... Verify accuracy of product drawings and ensure proper usage of Geometric Dimensioning and ...

next page

Showing results 1-20

Design Verification Engineer information

See Pennsylvania salary details

$105.8K

$149.5K

$167.4K

How much do design verification engineer jobs pay per year?

As of Jul 28, 2026, the average yearly pay for design verification engineer in Pennsylvania is $149,508.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,300.00 and $166,400.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Design Verification Engineer position, and why are they important?

Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.

What is a Design Verification Engineer job?

A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.

What are the most common challenges faced by Design Verification Engineers in their daily work?

Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.

What are the most commonly searched types of Design Verification Engineer jobs in Pennsylvania? The most popular types of Design Verification Engineer jobs in Pennsylvania are:
What are popular job titles related to Design Verification Engineer jobs in Pennsylvania? For Design Verification Engineer jobs in Pennsylvania, the most frequently searched job titles are:
What job categories do people searching Design Verification Engineer jobs in Pennsylvania look for? The top searched job categories for Design Verification Engineer jobs in Pennsylvania are:
What cities in Pennsylvania are hiring for Design Verification Engineer jobs? Cities in Pennsylvania with the most Design Verification Engineer job openings:
What are popular job titles related to Design Verification Engineer jobs in PA? For Design Verification Engineer jobs in PA, the most frequently searched job titles are:
Infographic showing various Design Verification Engineer job openings in Pennsylvania as of July 2026, with employment types broken down into 80% Full Time, 14% Part Time, 1% Temporary, 4% Contract, and 1% Nights. Highlights an 84% Physical, 6% Hybrid, and 10% Remote job distribution, with an average salary of $149,508 per year, or $71.9 per hour.
Design verification Engineer

Design verification Engineer

Scadea Solutions Inc

Allentown, PA • On-site

$134K - $163K/yr

Full-time

Posted 19 days ago


Job description

Company Description
About Us :
Scadea Solutions is a global talent acquisition and executive search company. We work exclusively with some of the most reputed and admired clients across various sectors and geographies. This is a very urgent role.
Job Description
Role- Design verification Engineer
Location - Allentown, PA
Duration - Full-time
Visa Status - US Citizen / Green Card
Description:
As a design verification engineer, you will be responsible for understanding expected design functionality, Develop test plans and functional validation tests to verify system will meet design requirements. You will be working closely with design engineers, architects and other team members to ensure high quality test plans and flawless test plan execution.
Minimum Qualifications:
• 5+ years of related industry experience in ASIC/SOC verification
• Must have hands-on experience and expert level knowledge on HVL based verification
Duties:
• Subsystem Level & SoC Level verification
• Verification plan creation for various blocks
• Enhance Test Bench if needed
• Develop the SoC/Subsystem Test case suite in various stages like RTL,GLS releases.
• Integrate System Verilog, OVM Test bench components like Scoreboard, Monitors and Bus Function Models.
• Develop System Level Scenario's for full Chip.
• Debug the complex chip simulations and deliver bug free chip
• Perform Code and functional coverage analysis for Various Subsystems
• Meet Quality requirements before various RTL release stages
Nice to have:
• Working experience of git version management tool
• Working experience on VCS, Questa CDC, Verdi
• Ability to deliver high quality output against deadlines and to
• work effectively in cross-site team environment
Qualifications
Additional Information
Required Skills:
Job Description:
Performs highly complex application programming/systems development and support Performs highly complex configuration of business rules and technical parameters of software products Review business requirements and develop application design documentation Build technical components (Maximo objects, TRM Rules, Java extensions, etc) based on detailed design.
Performs unit testing of components along with completing necessary documentation. Supports product test, user acceptance test, etc as a member of the fix-it team. Employs consistent measurement techniques Include testing in project plans and establish controls to require adherence to test plans Manages the interrelationships among various projects or work objectives