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Design For Test Dft Engineer Jobs in California (NOW HIRING)

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

... in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC ...

Apple

Design for Test Engineer

Cupertino, CA · On-site

$146K - $218K/yr

Implement DFT infrastructure. Code Verilog Register Transfer Language (RTL) for DFT logic ... Engage with test engineers to debug and bring up test vectors on silicon. Support TTR (Test time ...

Meta

ASIC Engineer, Design for Test

Sunnyvale, CA · On-site

$146K - $209K/yr

As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at ...

Apple

Design for Test Engineer

Cupertino, CA · On-site

$146K - $218K/yr

Implement DFT infrastructure. Code Verilog Register Transfer Language (RTL) for DFT logic ... Engage with test engineers to debug and bring up test vectors on silicon. Support TTR (Test time ...

Apple Inc.

Design for Test Engineer

Cupertino, CA · On-site

$146K - $218K/yr

Implement DFT infrastructure. Code Verilog Register Transfer Language (RTL) for DFT logic ... Engage with test engineers to debug and bring up test vectors on silicon. Support TTR (Test time ...

Broadcom Inc.

DFT Engineer

San Jose, CA · On-site

... design-for-test (DFT) structures, and establish baseline yield limits. * Cross functional: Work ... Must be a self‑driven engineer with good project management and organizational skills to deliver ...

Cisco

ASIC DFT Engineer

San Jose, CA · On-site

$167K - $245K/yr

Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in ... Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 ...

Nvidia Corporation

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

MS/PhD or equivalent experience in Electrical Engineering or a related field * 6+ years of hands-on experience in Design-For-Test (DFT) * Deep knowledge of DFT tools, methodologies, and test ...

Broadcom

DFT Engineer

San Jose, CA · On-site

... design-for-test (DFT) structures, and establish baseline yield limits. * Cross functional: Work ... Must be a self-driven engineer with good project management and organizational skills to deliver ...

QFocus Technologies LLC

DFT Engineer

Sunnyvale, CA · On-site

As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work ...

Nvidia

Senior DFT Engineer

Santa Clara, CA · Hybrid

$122K - $168K/yr

MS/PhD or equivalent experience in Electrical Engineering or a related field * 6+ years of hands-on experience in Design-For-Test (DFT) * Deep knowledge of DFT tools, methodologies, and test ...

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All JobsDesign For Test Dft Engineer JobsDesign For Test Dft Engineer Jobs in California

Design For Test Dft Engineer information

What is the difference between Design For Test Dft Engineer vs Test Development Engineer?

AspectDesign For Test (Dft) EngineerTest Development Engineer
Primary FocusDesigning testability features into chips and circuitsDeveloping and executing test plans and procedures for products
Skills & CertificationsASIC/FPGA design, EDA tools, verification, scriptingTest equipment, automation, scripting, hardware troubleshooting
Work EnvironmentSemiconductor companies, IC design teamsElectronics manufacturing, product testing labs

While both roles involve testing, a Design For Test Engineer focuses on embedding test features during chip design, ensuring manufacturability. A Test Development Engineer concentrates on creating and executing tests for finished products. Both roles require strong technical skills but differ in their stage of involvement in the product lifecycle.

What cities in California are hiring for Design For Test Dft Engineer jobs?

Cities in California with the most Design For Test Dft Engineer job openings:

Design For Test Dft Engineer jobs near you
Infographic showing various Design For Test Dft Engineer job openings in California as of August 2026, with employment types broken down into 91% Full Time, 6% Part Time, and 3% Contract. Highlights an 82% Physical, 5% Hybrid, and 13% Remote job distribution.

ASIC DFT Engineer

Irvine, CA • On-site

Purple Hires Inc
See more jobs at Purple Hires Incexternal

Contractor

Re-posted 9 days ago

Job description

Job Description

Key skills for Lead ASIC DFT:

 

please see these key words of in the project description for the profile consideration.

  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.