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Design Engineer Pcie Jobs in Arizona (NOW HIRING)

Digital Design Engineer II

Tucson, AZ · On-site

$128K/yr

Raytheon's Hardware Electrical Engineering team is responsible for Design, Validation ... such as PCIe, Ethernet, I2C, SPI, and UART. * Travel Requirements: less than 10% annually ...

Raytheon's Hardware Electrical Engineering team is responsible for Design, Validation ... such as PCIe, Ethernet, I2C, SPI, and UART. * Travel Requirements: less than 10% annually ...

Raytheon's Hardware Electrical Engineering team is responsible for Design, Validation ... such as PCIe, Ethernet, I2C, SPI, and UART. * Travel Requirements: less than 10% annually ...

Raytheon's Hardware Electrical Engineering team is responsible for Design, Validation ... such as PCIe, Ethernet, I2C, SPI, and UART. * Travel Requirements: less than 10% annually ...

Advanced Packaging Design Engineer

Chandler, AZ · On-site

$133K/yr

Lead Si/package/PCB/system co-design work collaborating with downstream system design teams and ... Meet specifications for high-speed interfaces such as HBM, DDR, PCIe and SerDes. * Netlist ...

Staff Digital Systems Engineer Reporting To: Design Engineering Manager Work Schedule: Onsite ... Design, integrate, and verify high-speed digital interfaces such as DDR, PCIe, Ethernet, SerDes ...

Showing results 21-40

Design Engineer Pcie information

What is a design engineer PCIe?

Design Engineer PCIe jobs involve designing, developing, and testing hardware and systems that utilize PCI Express (PCIe) technology for high-speed data transfer. These engineers work on creating circuit boards, verifying PCIe interfaces, and ensuring compliance with industry standards. Their role often includes collaborating with software and hardware teams to optimize system integration and performance. Design Engineer PCIe professionals are crucial in industries like computing, networking, and storage solutions, where reliable and fast data communication is essential.

What are some typical challenges a design engineer PCIe faces when integrating PCIe interfaces into new hardware products?

As a Design Engineer PCIe, you will often encounter challenges related to ensuring signal integrity and compatibility when integrating PCIe interfaces into hardware designs. This can involve addressing issues like high-speed signal routing, managing power consumption, and ensuring compliance with PCIe standards. Collaboration with firmware, hardware, and verification teams is common to resolve interoperability issues and optimize performance. Staying updated on the latest PCIe specifications and debugging complex system-level problems are also key aspects of the role.

What are the key skills and qualifications needed to thrive as a design engineer PCIe, and why are they important?

To excel as a Design Engineer specializing in PCIe, you need a solid background in electrical or computer engineering, with expertise in high-speed digital design and thorough knowledge of PCI Express protocols. Proficiency with hardware design tools such as Cadence or Synopsys, simulation tools, and familiarity with industry standards like PCIe specifications are typically required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set top engineers apart. These competencies ensure robust, reliable hardware designs that meet performance standards and integrate seamlessly into complex systems.

What is the difference between Design Engineer Pcie vs Design Engineer Usb?

AspectDesign Engineer PcieDesign Engineer Usb
Required SkillsPCIe protocol, hardware design, FPGA/ASIC developmentUSB standards, hardware design, FPGA/ASIC development
Work EnvironmentSemiconductor companies, hardware development labsConsumer electronics, peripheral device companies
CertificationsRelevant hardware design certifications, industry experienceSimilar certifications, focus on interface standards

Both Design Engineer Pcie and Design Engineer Usb roles involve hardware interface design, requiring similar skills and certifications. The main difference lies in the specific protocols and standards they work with: PCIe for high-speed data transfer in computers and servers, and USB for peripheral connectivity. Their work environments and industry applications also differ, with PCIe roles often in enterprise hardware and USB roles in consumer electronics.

What cities in Arizona are hiring for Design Engineer Pcie jobs?

Cities in Arizona with the most Design Engineer Pcie job openings:

Infographic showing various Design Engineer Pcie job openings in Arizona as of June 2026, with employment types broken down into 91% Full Time, 8% Part Time, and 1% Contract. Highlights an 92% Physical, 5% Hybrid, and 3% Remote job distribution.

Technical Staff Engineer - Design

FHLB Des Moines

Chandler, AZ • On-site

$140 - $180/hr

Other

Posted 2 days ago

New


Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!

Job Description

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry’s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership. An opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip’s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won’t just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment you’d like to participate in, we’d like to hear from you!

  • Own design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.
  • Develop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.
  • Generate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams.
  • Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.
  • Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.
  • Support Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements.
Requirements & Qualifications
  • B.S degree in electrical engineering with 12+ years related experience.
  • Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
  • Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).
  • Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.
  • Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off.
  • Understanding of Foundation and Hard IP related views including RTL, lef and liberty.
  • Working proficiency in flow automation and scripting using tcl and/or python.
  • Excellent analytical, communication (written and verbal), and documentation skills.
  • Preferred qualifications:
    • M.S degree in electrical engineering.
    • Basic understanding of DFT methodologies mainly JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation for including post-silicon bring-up and debug flows for SoC IO validation.
    • Exposure to RTL compilation and Synthesis flow including understanding of Verilog/System Verilog is desirable.
    • Working knowledge of Industry standard Project management, versioning and tracking tools e.g. SVN, JIRA.
Travel Time

0% - 25%

Physical Attributes

Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements

80% sitting, 10% standing, 10% walking, 100% inside

Equal Employment Opportunity

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

Company Culture

At Microchip, employees are our greatest strength. As one of the top performing semiconductor companies in the world, we are led by a set of guiding values and a mission to empower innovation to enhance the human experience. We work tirelessly to create a company culture that highlights how important every employee is to our mission.

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