Digital Signal Processing/Forward Error Correction Engineer, Linthicum Heights, MD We are looking ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...
Digital Signal Processing/Forward Error Correction Engineer, Linthicum Heights, MD We are looking ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...
FPGA Electrical Engineer
Linthicum, MD · On-site
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
FPGA Electrical Engineer
Linthicum, MD · On-site
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
Aperio Global seeking an experienced senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Aperio Global seeking an experienced senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Senior FPGA Electrical Engineer
Linthicum, MD · On-site
$102K - $138K/yr
Senior FPGA Electrical Engineer, Linthicum Heights, MD We are looking for multiple Senior FPGA ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
Senior FPGA Electrical Engineer
Linthicum, MD · On-site
$102K - $138K/yr
Senior FPGA Electrical Engineer, Linthicum Heights, MD We are looking for multiple Senior FPGA ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
... engineers to oversee board bring-up. Candidates should be comfortable working in both a design and ... Firmware: Collaborate closely with RTL teams to define pinouts, bank voltages, and clocking ...
... engineers to oversee board bring-up. Candidates should be comfortable working in both a design and ... Firmware: Collaborate closely with RTL teams to define pinouts, bank voltages, and clocking ...
Senior FPGA Engineer
Fairfax, VA · On-site
$97K - $181K/yr
Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...
Quick apply
Senior FPGA Engineer
Fairfax, VA · On-site
$97K - $181K/yr
Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...
388 Senior Hardware/Software Design Engineer with Security Clearance
Annapolis Junction, MD · On-site
$167K - $187K/yr
388 Senior Hardware/Software Design Engineer Annapolis Junction, MD Hardware/Software Design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
388 Senior Hardware/Software Design Engineer with Security Clearance
Annapolis Junction, MD · On-site
$167K - $187K/yr
388 Senior Hardware/Software Design Engineer Annapolis Junction, MD Hardware/Software Design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Digital Design Engineer - Level 5 - Linthicum
Linthicum, MD · On-site
$185K - $278K/yr
Experience developing test plans, participating in reviews, test development and RTL debug * Must ... design options. * Experience with Systems Engineering principles Curious about all the exciting ...
Digital Design Engineer - Level 5 - Linthicum
Linthicum, MD · On-site
$185K - $278K/yr
Experience developing test plans, participating in reviews, test development and RTL debug * Must ... design options. * Experience with Systems Engineering principles Curious about all the exciting ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Senior FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
Senior FPGA Engineer, Linthicum Heights, MD We are looking for multiple candidates at multiple ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
Senior FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
Senior FPGA Engineer, Linthicum Heights, MD We are looking for multiple candidates at multiple ... partition design within ASIC/FPGA, create specification documents. - Develop RTL designs using ...
Digital Design Engineer - Level 5 - Linthicum
Linthicum, MD · On-site
$185K - $278K/yr
Experience developing test plans, participating in reviews, test development and RTL debug * Must ... design options. * Experience with Systems Engineering principles Curious about all the exciting ...
Digital Design Engineer - Level 5 - Linthicum
Linthicum, MD · On-site
$185K - $278K/yr
Experience developing test plans, participating in reviews, test development and RTL debug * Must ... design options. * Experience with Systems Engineering principles Curious about all the exciting ...
Senior Hardware/Software Design Engineer (HSDE-3)
Annapolis, MD · On-site
$131K - $237K/yr
Our talented team is at the forefront in Security Engineering, Computer Network Operations (CNO ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Senior Hardware/Software Design Engineer (HSDE-3)
Annapolis, MD · On-site
$131K - $237K/yr
Our talented team is at the forefront in Security Engineering, Computer Network Operations (CNO ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Our talented team is at the forefront in Security Engineering, Computer Network Operations (CNO ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Our talented team is at the forefront in Security Engineering, Computer Network Operations (CNO ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
Engineer
Fairfax, VA · On-site
... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...
388 Senior Hardware/Software Design Engineer
Annapolis Junction, MD · On-site
$167K - $187K/yr
ARSIEM is looking for a an experienced Senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Quick apply
388 Senior Hardware/Software Design Engineer
Annapolis Junction, MD · On-site
$167K - $187K/yr
ARSIEM is looking for a an experienced Senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
FPGA Verification Engineer with Security Clearance
Arlington, VA · On-site
$141K - $195K/yr
... Debug RTL failures in simulation and on hardware targets • Develop constrained-random and ... with design engineers on architecture reviews and interface specifications • Support hardware ...
FPGA Verification Engineer with Security Clearance
Arlington, VA · On-site
$141K - $195K/yr
... Debug RTL failures in simulation and on hardware targets • Develop constrained-random and ... with design engineers on architecture reviews and interface specifications • Support hardware ...
ARSIEM is looking for a an experienced Senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
ARSIEM is looking for a an experienced Senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
388 Senior Hardware/Software Design Engineer
Annapolis, MD · On-site
$167K - $187K/yr
ARSIEM is looking for a an experienced Senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
388 Senior Hardware/Software Design Engineer
Annapolis, MD · On-site
$167K - $187K/yr
ARSIEM is looking for a an experienced Senior HW/SW Design Engineer to join a small team to design ... This role combines hardware design responsibilities (FPGA RTL development, timing closure, resource ...
Cpu Rtl Design Engineer information
See Washington, DC salary details
$46K - $58.1K
2% of jobs
$58.1K - $70.3K
11% of jobs
$76.8K is the 25th percentile. Wages below this are outliers.
$70.3K - $82.5K
23% of jobs
The median wage is $90.3K / yr.
$82.5K - $94.6K
22% of jobs
$94.6K - $106.8K
17% of jobs
$107.2K is the 75th percentile. Wages above this are outliers.
$106.8K - $119K
9% of jobs
$119K - $131.2K
6% of jobs
$131.2K - $143.3K
3% of jobs
$143.3K - $155.5K
3% of jobs
$155.5K - $167.7K
2% of jobs
$167.7K - $179.9K
1% of jobs
$46K
$100K
$179.9K
How much do cpu rtl design engineer jobs pay per year?
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?
What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?
What are CPU RTL Design Engineers?
Full-time
Medical, Retirement, PTO
Re-posted 3 days ago
Job description
We are looking for multiple candidates at multiple levels for this Digital Signal Processing/Forward Error Correction Engineer position. Candidates must be US Citizens and cannot have Dual Citizenships. All candidates must be fully vaccinated with an FDA authorized and/or approved COVID-19 vaccine as a condition of employment. Requests for reasonable accommodations for medical, religious, or other reasons will be considered in accordance with applicable law. These positions are 100% Onsite.
Responsibilities:
- Familiarity with standard classes of codes, including BCH, Reed-Solomon, Reed-Muller, Golay Codes, Convolutional Codes, Turbo Codes, LDPCs, Polar Codes, etc.
- Ability to analyze systems and communication channels and choose modulation and coding (including code design, rates, puncturing schemes, etc) that are most appropriate to maximize performance.
- Contribute to algorithm design, analysis and architecture specification for DSP blocks of a digital front end various radio architectures.
- Derive requirements, conceptualize, define, design & prototype systems engineering solutions.
- Understand system-level requirements and work with various teams to ensure that designs and implementations are meeting expectations.
- Document designs and interfaces, distribute across teams and conduct reviews and discussions.
- Understand the big picture but also break down to system-level components to capture dependencies, bottlenecks or risk areas in design.
- Work with systems architects and hardware engineers to develop, implement and test robust radio signal processing algorithms.
- Test, verification and debug of field test systems.
Minimum Qualifications:
- Knowledge of modulation, demodulation, forward error correction, randomization, and packet analysis.
- Prior experience designing and/or building wireless communications transmitters and receivers.
- Familiar with design, optimization and testing of communication signal processing algorithms.
- Experience in writing Matlab and C/C++ to emulate system test conditions.
- Understanding of commercial standards (e.g., 802.11, 4G/5G, etc.).
- Proficient in Matlab, Mathematica, Python or other scripting language, simulation tools.
- Proficient in creating engineering documents: system designs, interface specifications, requirements/specifications, etc.
Preferred Qualifications:
- Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL).
- Good knowledge and understanding across various engineering principles that apply to wireless communications systems (RF, DSP, FPGA, software, digital/hardware, mechanical/packaging) and their interdependencies.
- Experience designing RF front-end architectures.
Benefits include medical insurance, retirement plan, PTO, etc. Salary: 80K+ DOE. Keywords: Linthicum Heights MD Jobs, Digital Signal Processing/Forward Error Correction Engineer, Matlab, C/C++, Mathematica, Python, FPGA, RTL Design, Verilog, System Verilog, VHDL, RF, DSP, Software, Digital Hardware, Engineering, Maryland Recruiters, Information Technology Jobs, IT Jobs, Maryland Recruiting
Looking to hire for similar positions in Linthicum Heights, MD or in other cities? Our IT recruiting agencies and staffing companies can help.
We help companies that are looking to hire Digital Signal Processing/Forward Error Correction Engineers for jobs in Linthicum Heights, Maryland and in other cities too. Please contact our IT recruiting agencies and IT staffing companies today! Phone 630-428-0600 ext. 11 or email us at jobs@nextstepsystems.com. Click here to submit your resume for this job and others.
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About Next Step Systems
Sourced by ZipRecruiter
Industry
It services
Company size
11 - 50 Employees
Headquarters location
Naperville, IL, US
Year founded
1995