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Cpu Rtl Design Engineer Jobs in Elizabeth, NJ (NOW HIRING)

Jane Street

Hardware Engineer (FPGA/ASIC)

New York, NY · On-site

... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...

City of New York

Desktop Design Engineer

Brooklyn, NY · On-site

Responsibilities : • Provide Engineering Design level support of desktop and laptop computers and ... CPU and storage when needed; • Diagnose and document problem resolution, provide Root Cause ...

Normal Computing

Hardware Engineer, FPGA

New York, NY · On-site

$200K - $400K/yr

As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...

City of New York

Desktop Design Engineer

Brooklyn, NY · On-site

$100K - $125K/yr

The Desktop Design Engineer is a key team member within the Enterprise Desktop Services Unit ... CPU and storage when needed; -Diagnose and document problem resolution, provide Root Cause Analysis ...

jobr.pro

Hardware Engineer, FPGA

Manhattan, NY · On-site

$100 - $130/hr

As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...

Knot

Senior Android Engineer

Manhattan, NY · On-site

... CPU usage, allocation behavior, concurrency, and rendering • Design stable public APIs and ... developers • Strengthen test coverage with unit tests, UI automation, integration tests, and ...

Knot

Senior Android Engineer

Manhattan, NY · On-site

... CPU usage, allocation behavior, concurrency, and rendering • Design stable public APIs and ... developers • Strengthen test coverage with unit tests, UI automation, integration tests, and ...

Knot

Senior iOS Engineer

Manhattan, NY · On-site

$154K/yr

... design, and optimization of the iOS SDK • Profile, debug, and improve memory usage, CPU ... developers integrating our SDK • Strengthen test coverage with unit tests, UI automation ...

Open Systems Technologies

C++ Developer

Manhattan, NY · On-site

$300K/yr

... a software engineer to help architect, design, and implement low latency C systems ... Understanding of CPU architecture with the ability to leverage CPU capabilities * Extensive ...

Qube Research & Technologies

FPGA Engineer

New York, NY

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

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Showing results 21-40

All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Elizabeth, NJ

Cpu Rtl Design Engineer information

See Elizabeth, NJ salary details

$40.8K

$88.7K

$159.5K

How much do cpu rtl design engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for cpu rtl design engineer in Elizabeth, NJ is $88,716.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,400.00 and $99,100.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Elizabeth, NJ?

For Cpu Rtl Design Engineer jobs in Elizabeth, NJ, the most frequently searched job titles are:

What job categories do people searching Cpu Rtl Design Engineer jobs in Elizabeth, NJ look for?

The top searched job categories for Cpu Rtl Design Engineer jobs in Elizabeth, NJ are:

What cities near Elizabeth, NJ are hiring for Cpu Rtl Design Engineer jobs?

Cities near Elizabeth, NJ with the most Cpu Rtl Design Engineer job openings:

Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Elizabeth, NJ as of June 2026, with employment types broken down into 90% Full Time, 9% Part Time, and 1% Contract. Highlights an 92% Physical, 5% Hybrid, and 3% Remote job distribution, with an average salary of $88,716 per year, or $42.7 per hour.

Hardware Engineer, Physical Design

Normal Computing

New York, NY • On-site

$200K - $400K/yr

Full-time

Posted 21 days ago

Job description

About Normal Computing
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
The Role
As a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow-optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.
We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures.
What You Will Own
  • Physical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).
  • Timing Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.
  • Power, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis.
  • Physical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.
  • Design & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility.
  • Tapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.

What Makes You a Great Fit
  • Tapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes.
  • PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure.
  • Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.
  • Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.

Bonus Points
  • Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles.
  • Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration).
  • Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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