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Cpu Rtl Design Engineer Jobs in New Jersey (NOW HIRING)

QCi

FPGA Design Engineer

Hoboken, NJ · On-site

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

QCi

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

QUANTUM COMPUTING, INC.

FPGA Design Engineer

Hoboken, NJ · On-site +1

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering About Us ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

Logiqal

FPGA Engineer - Control Systems

Princeton, NJ · On-site

$150 - $235/hr

We're looking for a few visionary scientists and engineers to join our team, to move fast and blow ... You'll design, implement, and verify features across the control stack, from RTL through ...

EndoSec LLC

FPGA Engineer

Moorestown, NJ · On-site

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

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$41.1K

$89.5K

$160.9K

How much do cpu rtl design engineer jobs pay per year?

As of Aug 30, 2026, the average yearly pay for cpu rtl design engineer in New Jersey is $89,493.00, according to ZipRecruiter salary data. Most workers in this role earn between $69,000.00 and $100,000.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in New Jersey?

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The top searched job categories for Cpu Rtl Design Engineer jobs in New Jersey are:

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Cities in New Jersey with the most Cpu Rtl Design Engineer job openings:

Cpu Rtl Design Engineer jobs near you

Senior Engineer, Physical Design Engineering (ASIC)

Analog Devices

Somerset, NJ • On-site

$143K - $147K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 2 days ago

Analog Devices rating

8.7

Company rating: 8.7 out of 10

Based on 19 frontline employees who took The Breakroom Quiz

18th of 159 rated electronics manufacturers

Job description

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
About the Role
As a Senior Physical Design Engineer, you will play a key role in the implementation and delivery of complex digital and mixed-signal IC designs. You will work across the physical design flow, from floorplanning through place-and-route, timing closure, physical verification, and tapeout support, helping turn architectural and RTL intent into robust silicon implementation. This role requires strong technical depth in physical design, the ability to solve complex implementation challenges, and effective collaboration with cross-functional teams across the development cycle.
Key Responsibilities
  • Own physical design implementation for complex digital blocks and subsystems, including floorplanning, placement, clock tree synthesis, routing, and physical optimization
  • Drive timing closure, congestion analysis, power optimization, and area improvement across assigned blocks or subsystems
  • Perform physical verification activities including DRC, LVS, ERC, and reliability checks in collaboration with relevant teams
  • Develop and refine physical design constraints, scripts, and flow improvements to improve quality and execution efficiency
  • Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve design and implementation issues
  • Support block-level and top-level integration activities, including interface planning, timing constraint alignment, and implementation readiness
  • Analyze and debug timing, signal integrity, power, and physical implementation issues across the full backend flow
  • Contribute to methodology improvements and help establish best practices for physical design execution
  • Participate in design reviews and provide clear technical input on implementation trade-offs, risks, and readiness
  • Author and maintain documentation for design implementation, constraints, flows, and signoff status
  • Mentor junior engineers on physical design practices, tool usage, and debugging approaches
  • Support tapeout planning and execution activities to ensure high-quality delivery against project milestones

Must Have Skills
  • Strong experience in physical design for ASIC/SoC development, including successful implementation through tapeout
  • Expertise in floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verification
  • Strong understanding of timing analysis, constraints, signal integrity, power optimization, and physical design trade-offs
  • Experience with industry-standard physical design and signoff tools, including Cadence-based flows
  • Scripting experience in TCL, Python, or similar languages for automation and flow improvement
  • Experience collaborating across cross-functional teams including RTL, STA, DFT, design verification, and package or product engineering
  • Strong problem-solving and debug skills across backend implementation challenges
  • Clear communication and technical documentation skills
  • Demonstrated ability to independently drive complex blocks or major implementation workstreams

Preferred Qualifications
  • Experience with advanced-node implementation and low-power design methodologies
  • Familiarity with mixed-signal integration considerations and top-level implementation challenges
  • Experience improving backend flows, automation, or methodology
  • Prior mentoring experience or informal technical leadership on project execution

Preferred Education and Experience
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experience
  • Master's degree in Electrical Engineering, Computer Engineering, or related field, or an equivalent combination of education and 5+ years of related experience

We recognize that candidates may not meet every listed requirement. If you bring relevant experience and a willingness to learn, we encourage you to apply.
#LI-PG1
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
The expected wage range for a new hire into this position is $116,960 to $160,820.
  • Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
  • This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
  • This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

What Analog Devices employees say

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Hours and flexibility

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About Analog Devices

Sourced by ZipRecruiter

Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.

Industry

Electrical equipment, appliance, and component manufacturing

Company size

5,001 - 10,000 Employees

Headquarters location

Norwood, MA, US

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