DFT Design Engineer
Boxborough, MA · Hybrid
As a Design-for-Testability (DFT) Engineer at AMD, you will own the full DFT lifecycle--from ... Proficiency with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design. * Exposure to ...
DFT Design Engineer
Boxborough, MA · Hybrid
As a Design-for-Testability (DFT) Engineer at AMD, you will own the full DFT lifecycle--from ... Proficiency with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design. * Exposure to ...
We are seeking an experienced, self-motivated, and passionate engineer to lead, architect, and ... RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems ...
We are seeking an experienced, self-motivated, and passionate engineer to lead, architect, and ... RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems ...
Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As a software engineer ...
Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As a software engineer ...
We're seeking a talented Hardware Design Engineer to contribute to the development and verification ... Write and verify RTL code for high-performance hardware components. * Support hardware bring-up and ...
Quick apply
Apply Early
We're seeking a talented Hardware Design Engineer to contribute to the development and verification ... Write and verify RTL code for high-performance hardware components. * Support hardware bring-up and ...
Apply Early
... Design Engineering to build and lead a PD organization from the ground up. This is a highly ... Strong experience collaborating with architecture, RTL design, packaging, and system teams on ...
... Design Engineering to build and lead a PD organization from the ground up. This is a highly ... Strong experience collaborating with architecture, RTL design, packaging, and system teams on ...
Implement in RTL and debug while collaborating with the verification team to ensure that the design ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...
Implement in RTL and debug while collaborating with the verification team to ensure that the design ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Waltham, MA · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
CPU Core Design Verification Engineer
Boxborough, MA · On-site
$106K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
CPU Core Design Verification Engineer
Boxborough, MA · On-site
$106K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
CPU Core Design Verification Engineer
Boxborough, MA · Hybrid
$131K - $160K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
CPU Core Design Verification Engineer
Boxborough, MA · Hybrid
$131K - $160K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
Digital IC Design Engineer - Early Career
Westborough, MA · On-site
$140K/yr
The team works across Architecture, RTL, Verification, Physical Design disciplines to deliver high ... Work with Architects and Verification Engineers to develop complex, high performance and timing ...
Digital IC Design Engineer - Early Career
Westborough, MA · On-site
$140K/yr
The team works across Architecture, RTL, Verification, Physical Design disciplines to deliver high ... Work with Architects and Verification Engineers to develop complex, high performance and timing ...
The team works across Architecture, RTL, Verification, Physical Design disciplines to deliver high ... Work with Architects and Verification Engineers to develop complex, high performance and timing ...
The team works across Architecture, RTL, Verification, Physical Design disciplines to deliver high ... Work with Architects and Verification Engineers to develop complex, high performance and timing ...
CPU Core Physical Design Engineer
Boxborough, MA · Hybrid
$39 - $44.50/hr
In this role, you'll contribute to high-speed logic design and physical implementation of a microprocessor core, collaborating with engineers across the design flow to meet timing, power, and ...
CPU Core Physical Design Engineer
Boxborough, MA · Hybrid
$39 - $44.50/hr
In this role, you'll contribute to high-speed logic design and physical implementation of a microprocessor core, collaborating with engineers across the design flow to meet timing, power, and ...
Sr. Silicon Design Engineer
Boxborough, MA · On-site
$106K/yr
Work with RTL engineers to resolve design defects and correct any test issues. Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage ...
Sr. Silicon Design Engineer
Boxborough, MA · On-site
$106K/yr
Work with RTL engineers to resolve design defects and correct any test issues. Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage ...
Timing Design Engineer
$116K - $203K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
$116K - $203K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
$165K - $292K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
$165K - $292K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
ASIC & FPGA Design Engineer Senior Staff
Andover, MA · On-site
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Defining FPGA architecture, writing clean RTL (VHDL/Verilog/SystemVerilog), and producing complete ...
ASIC & FPGA Design Engineer Senior Staff
Andover, MA · On-site
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Defining FPGA architecture, writing clean RTL (VHDL/Verilog/SystemVerilog), and producing complete ...
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertionbased ...
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertionbased ...
Cpu Rtl Design Engineer information
See Massachusetts salary details
$44.2K - $55.9K
2% of jobs
$55.9K - $67.7K
11% of jobs
$73.9K is the 25th percentile. Wages below this are outliers.
$67.7K - $79.4K
23% of jobs
The median wage is $86.9K / yr.
$79.4K - $91.1K
22% of jobs
$91.1K - $102.8K
17% of jobs
$103.1K is the 75th percentile. Wages above this are outliers.
$102.8K - $114.5K
9% of jobs
$114.5K - $126.2K
6% of jobs
$126.2K - $138K
3% of jobs
$138K - $149.7K
3% of jobs
$149.7K - $161.4K
2% of jobs
$161.4K - $173.1K
1% of jobs
$44.2K
$96.3K
$173.1K
How much do cpu rtl design engineer jobs pay per year?
As of Jul 5, 2026, the average yearly pay for cpu rtl design engineer in Massachusetts is $96,270.00, according to ZipRecruiter salary data. Most workers in this role earn between $74,300.00 and $107,600.00 per year, depending on experience, location, and employer.
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?
CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.
What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?
To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.
What are CPU RTL Design Engineers?
CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Massachusetts? For Cpu Rtl Design Engineer jobs in Massachusetts, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Massachusetts look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Massachusetts are:
What cities in Massachusetts are hiring for Cpu Rtl Design Engineer jobs? Cities in Massachusetts with the most Cpu Rtl Design Engineer job openings:
Advanced Micro Devices rating
8.4
Based on 7 frontline employees who took The Breakroom Quiz
22nd of 141 rated electronics manufacturers
Job description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a Design-for-Testability (DFT) Engineer at AMD, you will own the full DFT lifecycle—from specification definition through post-silicon bring-up—to ensure robust and efficient test solutions. You will collaborate closely with Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers, and Program Management to deliver successful and timely project outcomes.
THE PERSON:
As part of AMD’s Strategic Silicon Solutions (S3) Business Unit, you will help bring customer-specific design requirements to life across a wide range of products, including tablets, gaming consoles, servers, and more. You thrive in a collaborative team environment, take ownership of tasks through to completion, and communicate effectively both verbally and in writing.
KEY RESPONSIBILITIES:
Implement and verify DFT and Design-for-Debug (DFD) architectures and features.
Insert Scan, JTAG, and Boundary Scan chains; generate ATPG patterns.
Generate, implement, and verify Memory Built-In Self-Test (BIST) logic.
Apply low power DFT techniques to designs.
Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
Analyze test coverage and work on reducing test costs.
Provide post-silicon support to ensure successful bring-up and improve yield learning.
PREFERRED EXPERIENCE:
- Strong understanding of Design For Test methodologies and DFT verification (e.g., IEEE1500, JTAG 1149.x, scan, memory BIST).
- Experience with Tessent TestKompress and Silicon Scan Network (SSN).
- Proficiency with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
- Exposure to static timing analysis and timing closure processes.
- Experience in pre-silicon test planning, validation, and engagement with design teams.
- Skilled in characterization and debugging of scan/ATPG tests in new silicon designs and process technologies.
- Expertise in optimizing test flows for quality enhancement and cost reduction.
- Ability to analyze part failures to improve test coverage and yield.
- Experience analyzing characterization data across process, voltage, and temperature (PVT) corners.
- Excellent communication skills and ability to work effectively in a global team environment.
- Knowledge of low power design concepts such as clock gating and power gating is a plus.
ACADEMIC CREDENTIALS:
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
LOCATIONS: Boxborough, MA, Austin, TX, and Markham, ON
This role is not eligible for Visa Sponsorship.
#LI-LC3
#LI-HYBRID
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Qualifications:Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Education:UNAVAILABLEEmployment Type: FULL_TIMEWhat Advanced Micro Devices employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US