Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As a software engineer ...
Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As a software engineer ...
We're seeking a talented Hardware Design Engineer to contribute to the development and verification ... Write and verify RTL code for high-performance hardware components. * Support hardware bring-up and ...
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We're seeking a talented Hardware Design Engineer to contribute to the development and verification ... Write and verify RTL code for high-performance hardware components. * Support hardware bring-up and ...
Timing Design Engineer
Waltham, MA · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Waltham, MA · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
ASIC Physical Design Engineer
$135K - $195K/yr
Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of ... Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) * Perform ...
ASIC Physical Design Engineer
$135K - $195K/yr
Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of ... Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) * Perform ...
ASIC Physical Design Engineer
$135K - $195K/yr
Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of ... Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) * Perform ...
ASIC Physical Design Engineer
$135K - $195K/yr
Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of ... Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) * Perform ...
ASIC Physical Design Engineer
Maynard, MA · On-site
$135K - $195K/yr
Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of ... Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) * Perform ...
ASIC Physical Design Engineer
Maynard, MA · On-site
$135K - $195K/yr
Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of ... Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) * Perform ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ... Mentoring junior engineers, sharing best practices, and fostering an inclusive, high performance ...
Timing Design Engineer
Waltham, MA · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
Waltham, MA · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
CPU Core Design Verification Engineer
Boxborough, MA · On-site
$106K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
CPU Core Design Verification Engineer
Boxborough, MA · On-site
$106K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
CPU Core Design Verification Engineer
Boxborough, MA · Hybrid
$131K - $160K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
CPU Core Design Verification Engineer
Boxborough, MA · Hybrid
$131K - $160K/yr
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design * Write tests, sequences, and testbench components in C++, x86 ...
CPU Core Physical Design Engineer
Boxborough, MA · Hybrid
$39 - $44.50/hr
In this role, you'll contribute to high-speed logic design and physical implementation of a microprocessor core, collaborating with engineers across the design flow to meet timing, power, and ...
CPU Core Physical Design Engineer
Boxborough, MA · Hybrid
$39 - $44.50/hr
In this role, you'll contribute to high-speed logic design and physical implementation of a microprocessor core, collaborating with engineers across the design flow to meet timing, power, and ...
Timing Design Engineer
$114K - $199K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
$114K - $199K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
ASIC & FPGA Design Engineer Senior Staff
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Defining FPGA architecture, writing clean RTL (VHDL/Verilog/SystemVerilog), and producing complete ...
ASIC & FPGA Design Engineer Senior Staff
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Defining FPGA architecture, writing clean RTL (VHDL/Verilog/SystemVerilog), and producing complete ...
Timing Design Engineer
$162K - $286K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Timing Design Engineer
$162K - $286K/yr
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)
Reading, MA · On-site
$98K - $157K/yr
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertion-based ...
ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)
Reading, MA · On-site
$98K - $157K/yr
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertion-based ...
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertionbased ...
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertionbased ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Your responsibilities will include: • Defining FPGA architecture, writing RTL (VHDL/Verilog ...
FPGA Design Engineer Staff
Andover, MA · On-site
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Your responsibilities will include: • Defining FPGA architecture, writing RTL (VHDL/Verilog ...
ASIC & FPGA Design Engineer Senior Staff
Andover, MA · On-site
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Defining FPGA architecture, writing clean RTL (VHDL/Verilog/SystemVerilog), and producing complete ...
ASIC & FPGA Design Engineer Senior Staff
Andover, MA · On-site
$124K - $171K/yr
You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Defining FPGA architecture, writing clean RTL (VHDL/Verilog/SystemVerilog), and producing complete ...
ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertion-based ...
ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)
Reading, MA · On-site
$123K - $196K/yr
Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic ... Experience with RTL design using Verilog HDL * Familiarity with System Verilog assertion-based ...
Cpu Rtl Design Engineer information
See Massachusetts salary details
$44.2K - $55.9K
2% of jobs
$55.9K - $67.7K
11% of jobs
$73.9K is the 25th percentile. Wages below this are outliers.
$67.7K - $79.4K
23% of jobs
The median wage is $86.9K / yr.
$79.4K - $91.1K
22% of jobs
$91.1K - $102.8K
17% of jobs
$103.1K is the 75th percentile. Wages above this are outliers.
$102.8K - $114.5K
9% of jobs
$114.5K - $126.2K
6% of jobs
$126.2K - $138K
3% of jobs
$138K - $149.7K
3% of jobs
$149.7K - $161.4K
2% of jobs
$161.4K - $173.1K
1% of jobs
$44.2K
$96.3K
$173.1K
How much do cpu rtl design engineer jobs pay per year?
As of Jun 14, 2026, the average yearly pay for cpu rtl design engineer in Massachusetts is $96,270.00, according to ZipRecruiter salary data. Most workers in this role earn between $74,300.00 and $107,600.00 per year, depending on experience, location, and employer.
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?
CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.
What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?
To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.
What are CPU RTL Design Engineers?
CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Massachusetts? For Cpu Rtl Design Engineer jobs in Massachusetts, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Massachusetts look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Massachusetts are:
What cities in Massachusetts are hiring for Cpu Rtl Design Engineer jobs? Cities in Massachusetts with the most Cpu Rtl Design Engineer job openings:
Job description
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new challenges that are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today!
Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes.
What You'll be Doing:
Work as a team to build reliable, scalable and high performance software that are easy to use by hundreds of engineers worldwide.
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs).
Research and develop software solutions to allow greater efficiency in architecture, hardware and software teams.
Optimize the daily workflows of the world's top chip modelers and designers.
What We Need to See:
BS (or equivalent experience) and 5+ years of software development experience., MS (or PHD) preferred.
Experienced with C++ or Golang, Unix/Linux.
Solid understanding of algorithms, computer architecture and computer science theory
Experienced with VLSI frontend design and verification
Flexibility/adaptability for working in a global and dynamic environment with different frameworks and requirements
Ways to stand out from the crowd:
Good architecture and RTL design knowledge
Strong expertise in modern C++, compiler, build systems, and database.
Experienced with static and dynamic code analysis tools
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993