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Computer Chip Designer Jobs in California (NOW HIRING)

Senior VLSI CAD Software Engineer

Santa Clara, CA · On-site

$143K - $189K/yr

... chip design and visualization tools, with possible tasks ranging from modeling to algorithms • ... innovative, well-designed, high-quality new code for desktop engineering applications • ...

Senior Photonic Device Designer

Santa Clara, CA · On-site

$119K - $128K/yr

... computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited ... Conduct chip layout circuit design, circuit checking, and device evaluation and characterization.

Passionate about well-designed software that is modifiable, efficient, reliable and meets coding ... computer chip built in the world. Nova dives deep into dimensions and layers at the atomic level to ...

$251K/yr

Work with the physical design and CAD team to resolve implementation level details. * Help mentor ... Familiarity with different on-chip network topologies: mesh, ring, crossbar. * Experience in ...

ASIC Architect

San Jose, CA · On-site

$200K - $265K/yr

... chip designs from concept to silicon. Key Responsibilities * Design and analyze chip architectures ... PhD in Computer Science, Electrical Engineering, Computer Engineering, or related field * 5+ years ...

Passionate about well-designed software that is modifiable, efficient, reliable and meets coding ... computer chip built in the world. Nova dives deep into dimensions and layers at the atomic level to ...

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Computer Chip Designer information

See California salary details

$9

$40

$99

How much do computer chip designer jobs pay per hour?

As of Jun 23, 2026, the average hourly pay for computer chip designer in California is $40.76, according to ZipRecruiter salary data. Most workers in this role earn between $17.31 and $57.64 per hour, depending on experience, location, and employer.

How much money do chip designers make?

Computer chip designers typically earn between $80,000 and $150,000 annually, depending on experience, education, and location. Senior designers with specialized skills or working in high-cost areas can earn higher salaries, and many roles require knowledge of hardware description languages and electronic design automation tools.

What are the key skills and qualifications needed to thrive as a Computer Chip Designer, and why are they important?

To thrive as a Computer Chip Designer, you need a strong background in electrical engineering, circuit design, and semiconductor physics, typically supported by a relevant engineering degree. Proficiency in hardware description languages (such as VHDL or Verilog), CAD tools like Cadence or Synopsys, and knowledge of EDA (Electronic Design Automation) systems are essential. Strong problem-solving abilities, attention to detail, and effective teamwork skills help designers succeed in complex, collaborative projects. These combined skills ensure that chip designs are innovative, efficient, and meet stringent performance and reliability standards in a competitive industry.

What is the difference between Computer Chip Designer vs Hardware Engineer?

AspectComputer Chip DesignerHardware Engineer
CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fieldsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields
Work EnvironmentDesign labs, CAD software, simulation toolsDevelopment labs, testing facilities, manufacturing environments
Industry UsageSemiconductor companies, tech firms, research institutionsElectronics manufacturing, product development, tech companies
Search & Comparison IntentOften compared for design focus and specializationBroader engineering roles involving hardware development

Computer Chip Designers focus on creating the architecture and design of integrated circuits using specialized software, while Hardware Engineers work on developing, testing, and implementing electronic hardware systems. Both roles require similar educational backgrounds and often collaborate, but their primary responsibilities differ in scope and focus.

What are some common challenges faced by computer chip designers in collaborative projects?

Computer chip designers often work closely with cross-functional teams, including hardware engineers, software developers, and verification specialists. One common challenge is ensuring clear communication and alignment across these diverse groups, especially when integrating complex design requirements and meeting tight deadlines. Additionally, balancing innovation with strict industry standards and manufacturing constraints can require careful negotiation and problem-solving. Adapting quickly to changes in project scope or technology is also a frequent challenge, making flexibility and teamwork essential for success.

What does a Computer Chip Designer do?

A Computer Chip Designer is responsible for creating the architecture and layout of microchips used in computers, smartphones, and other electronic devices. They use specialized software to design, simulate, and test integrated circuits to ensure they meet performance, power, and size requirements. The job involves close collaboration with hardware engineers, testing teams, and manufacturers to bring innovative chip designs from concept to production. Computer Chip Designers play a critical role in advancing technology by making devices faster, more efficient, and more capable.

How hard is it to get into chip design?

Getting into chip design as a computer chip designer typically requires a strong background in electrical engineering or computer science, often including a bachelor's degree at minimum and advanced knowledge of digital logic, VLSI design, and CAD tools. Entry can be competitive, with many positions favoring candidates with internships, relevant certifications, or a master's degree. Developing skills in programming languages like Verilog or VHDL and gaining experience with chip design software can improve job prospects.

Is chip design a good career?

Computer chip design is a specialized engineering field that involves developing integrated circuits and microprocessors, requiring skills in electronics, programming, and CAD tools. It offers high demand, competitive salaries, and opportunities for innovation, especially in industries like consumer electronics, automotive, and telecommunications.

What engineers make $500,000?

Senior computer chip designers, especially those with extensive experience, advanced skills in hardware architecture, and expertise in tools like VHDL or Verilog, can earn salaries of $500,000 or more annually. Such high compensation often includes bonuses, stock options, and other incentives, typically found in leading technology companies or specialized semiconductor firms.
What are popular job titles related to Computer Chip Designer jobs in California? For Computer Chip Designer jobs in California, the most frequently searched job titles are:
What job categories do people searching Computer Chip Designer jobs in California look for? The top searched job categories for Computer Chip Designer jobs in California are:
What cities in California are hiring for Computer Chip Designer jobs? Cities in California with the most Computer Chip Designer job openings:
Infographic showing various Computer Chip Designer job openings in California as of June 2026, with employment types broken down into 50% As Needed, and 50% Full Time. Highlights an 88% Physical, 2% Hybrid, and 10% Remote job distribution, with an average salary of $84,781 per year, or $40.8 per hour.
SOC Physical Design Static Timing Analysis Engineer

SOC Physical Design Static Timing Analysis Engineer

Intel

Santa Clara, CA • On-site

$164K - $311K/yr

Full-time

Medical, Retirement, PTO

Posted 25 days ago


Intel rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

10th of 139 rated electronics manufacturers


Job description

Job Details:Job Description: 

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. Collaborating across multiple teams, you will contribute to the creation and optimization of high-performance, low-power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today's world and inspire tomorrow's possibilities.

Key Responsibilities:

  • Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
  • Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
  • Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
  • Define methodologies to produce high-quality timing models and enable efficient physical design execution.
  • Establish the appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans, and binning strategies.
  • Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
  • Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
  • Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.
Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

  • Bachelor's degree with 8 +years or master's degree with 6+ years or PhD with 4+ years in Electrical Engineering or Computer Engineering or Computer Science or a related field.
  • 7+ years technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
  • 3+ years of experience with the following skills:
  • Strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques.
  • Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.

Preferred Skills/Experience:

  • Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs.
  • Experience with SoC clocking methodologies, disciplined execution, and problem-solving in digital design.
  • Knowledge of tools, flows, and methodologies for high-performance physical design.
  • Strong communication skills and ability to articulate technical concepts effectively.
  • DFT architecture knowledge is a strong plus
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa ClaraBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968