Circuit Design Engineer Internship Jobs in Scottsdale, AZ

Job Details:Job Description: 

About the Team

The Design Technology Platform (DTP) is one of the key pillars-alongside Technology and Development and Foundry-enabling Intel to deliver winning products.

Our mission is to enable product design teams to reach market faster with leadership products on cutting-edge technologies.

Role Summary

As a member of the Advanced Design Foundation IP group in DTP, you will be at the forefront of designing critical foundational collateral on leading edge Intel processes to meet density and performance scaling goals of Intel CPU and SoC products. ADFIP serves as the design interface with the process development team working out key design process interactions for all new processes. These collaterals include Metal Finger Capacitors (MFC), Thin Film Resistors (TFR), inductors, varactors, transmission lines, and other passive components. You will collaborate closely with process/device, PDK/modeling, EDA, and product design teams to co-optimize design and technology (DTCO) and to deliver silicon proven solutions through test chips.

What You'll Do

Your responsibilities will include, but are not limited to:

• You will be responsible for driving on-time library PDK release with highest quality, coordinate with the design owners and multiple stake holders in device, integration, OPC, DR, and runset for customer solutions.
• Ensure the timely development and test coverage to cover possible design usage scenarios for passive component templates.
• Definition of copy exact foundational IP in collaboration with analog and RF designers in product groups and AD to support passive component needs while optimizing for performance, area, and process compatibility.
• Working with process device and reliability stake holders as part of DTCO to co-optimize design, process modeling and design rules for passive components.
• Designing library collateral schematics and layouts for passive components, and characterizing them through all PV RV and electrical parameter extraction flows.
• Develop and maintain template design guidelines and best practices for MFC, TFR, and other passive components across different process nodes.
• Collaborate with modeling teams to ensure accurate electrical models for designed templates.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in electrical engineering or related STEM field with 4+ years in analog/RF circuit design or device physics fundamentals. OR
• Master's degree in electrical engineering or related STEM field with 3+ years in analog/RF circuit design or device physics fundamentals. OR
• Ph.D. degree in electrical engineering or related STEM field with 6+ months of professional experience in analog/RF circuit design or device physics fundamentals.
• 3+ years' experience with SPICE level circuit design/simulation and Cadence Virtuoso (or equivalent custom design environment), including layout generation.
• 3+ years' experience in data analysis/scripting (e.g., Python or Matlab).

Preferred Qualifications:

• 1+ year of experience with device physics, analog fundamentals (gain, bandwidth, noise, linearity, stability), and/or variability/yield (corners, mismatch, Monte Carlo).

• Experience with passive component design and characterization (capacitors, resistors, inductors)
• Knowledge of electromagnetic simulation tools and RF design principles
• Familiarity with advanced process technologies and their impact on passive component performance
• Experience with Verilog modeling, EM/IR and reliability checks, or electromagnetic/RF simulation flows.
• Familiar with Pcell design using SKILL
• Exposure to post silicon characterization and debug
• Familiarity with statistics/DOE and machine learning for design space exploration or correlation
• Comfortable working across time zones with process, modeling, PDK, and product teams
• Strong communication, collaboration, and problem-solving skills.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa ClaraBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.