CA$138K - CA$220K/yr
Medical
Dental
Vision
Retirement
PTO
... chip,product bring-upand characterization. * Provide technical guidance and mentorship to more junior design and layout engineers, and report status and share experience with the group on a regular ...
CA$138K - CA$220K/yr
Medical
Dental
Vision
Retirement
PTO
... chip,product bring-upand characterization. * Provide technical guidance and mentorship to more junior design and layout engineers, and report status and share experience with the group on a regular ...
Responsibilities Design high-speed IC packages and Chip-On-Board (COB) solutions to meet new ... Mentor junior packaging engineers and contribute to continuous improvement of design methodologies ...
Responsibilities Design high-speed IC packages and Chip-On-Board (COB) solutions to meet new ... Mentor junior packaging engineers and contribute to continuous improvement of design methodologies ...
Responsibilities Design high-speed IC packages and Chip-On-Board (COB) solutions to meet new ... Mentor junior packaging engineers and contribute to continuous improvement of design methodologies ...
Responsibilities Design high-speed IC packages and Chip-On-Board (COB) solutions to meet new ... Mentor junior packaging engineers and contribute to continuous improvement of design methodologies ...
You'll be part of a team that drives innovation in custom chip development, directly impacting the ... We are looking for a passionate Design Verification Engineer to join our newly formed team ...
You'll be part of a team that drives innovation in custom chip development, directly impacting the ... We are looking for a passionate Design Verification Engineer to join our newly formed team ...
Toronto, ON · Hybrid
CA$99K - CA$135K/yr
Join the proactive Chip Methodology & Automation (CMA) team within Arm's Solutions Engineering organization! As a CAD-DFT Engineer, you will develop and apply scalable strategies, sequences, and ...
Toronto, ON · Hybrid
CA$99K - CA$135K/yr
Join the proactive Chip Methodology & Automation (CMA) team within Arm's Solutions Engineering organization! As a CAD-DFT Engineer, you will develop and apply scalable strategies, sequences, and ...
Our areas of expertise include Memory Compilers, High-Speed IOs, BIST/DFT, and Test-Chip design and ... Overview of Role The Digital Verification Engineer will work closely with design teams to validate ...
Our areas of expertise include Memory Compilers, High-Speed IOs, BIST/DFT, and Test-Chip design and ... Overview of Role The Digital Verification Engineer will work closely with design teams to validate ...
Our areas of expertise include Memory Compilers, High-Speed IOs, BIST/DFT, and Test-Chip design and ... Ensure engineers have optimal and reliable remote access to corporate data centers, troubleshooting ...
Our areas of expertise include Memory Compilers, High-Speed IOs, BIST/DFT, and Test-Chip design and ... Ensure engineers have optimal and reliable remote access to corporate data centers, troubleshooting ...
Toronto, ON · On-site
Medical
Dental
Vision
Life
Retirement
PTO
You will collaborate with worldclass design, verification, and process teams to deliver robust ... Own floor planning, blocklevel routing, and toplevel chip assembly activities for complex ...
Toronto, ON · On-site
Medical
Dental
Vision
Life
Retirement
PTO
You will collaborate with worldclass design, verification, and process teams to deliver robust ... Own floor planning, blocklevel routing, and toplevel chip assembly activities for complex ...
Kanata, ON · Hybrid
Medical
Dental
Vision
Life
Retirement
PTO
... engineers to collaborate in order to provide an optimized design that will integrate into the ASIC ... You will lead efforts for a large block on a complex chip, mentor team members and track ...
Kanata, ON · Hybrid
Medical
Dental
Vision
Life
Retirement
PTO
... engineers to collaborate in order to provide an optimized design that will integrate into the ASIC ... You will lead efforts for a large block on a complex chip, mentor team members and track ...
CA$131K - CA$171K/yr
Medical
Retirement
PTO
Work on high-impact design automation while continuing hands-on RF/EM design. * Balanced role ... Understanding of RF front-end modules and technologies including: -BAW/SAW filters -Multi-chip ...
CA$131K - CA$171K/yr
Medical
Retirement
PTO
Work on high-impact design automation while continuing hands-on RF/EM design. * Balanced role ... Understanding of RF front-end modules and technologies including: -BAW/SAW filters -Multi-chip ...
You'll be part of a team that drives innovation in custom chip development, directly impacting the ... We are looking for a passionate Design Verification Engineer to join our newly formed team ...
You'll be part of a team that drives innovation in custom chip development, directly impacting the ... We are looking for a passionate Design Verification Engineer to join our newly formed team ...
Toronto, ON · On-site
What You Can Expect ASIC design engineer responsible for post RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation and ECOs. The ...
Toronto, ON · On-site
What You Can Expect ASIC design engineer responsible for post RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation and ECOs. The ...
Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools * Knowledge of chip level integration and ESD concepts a plus * Perl programming, TCL and SKILL programming ...
Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools * Knowledge of chip level integration and ESD concepts a plus * Perl programming, TCL and SKILL programming ...
... the engineering team. This will require a solid understanding of process technology, state of the art in chip design, and clear communication skills. In this role, you will be defining the ...
... the engineering team. This will require a solid understanding of process technology, state of the art in chip design, and clear communication skills. In this role, you will be defining the ...
... the engineering team. This will require a solid understanding of process technology, state of the art in chip design, and clear communication skills. In this role, you will be defining the ...
... the engineering team. This will require a solid understanding of process technology, state of the art in chip design, and clear communication skills. In this role, you will be defining the ...
Ottawa, ON · On-site
Our areas of expertise include Memory Compilers, High-Speed IOs, BIST/DFT, and Test-Chip design and ... Overview of Role In the role of Senior Memory Layout Engineer, you will primarily be responsible ...
Ottawa, ON · On-site
Our areas of expertise include Memory Compilers, High-Speed IOs, BIST/DFT, and Test-Chip design and ... Overview of Role In the role of Senior Memory Layout Engineer, you will primarily be responsible ...
Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools * Knowledge of chip level integration and ESD concepts a plus * Perl programming, TCL and SKILL programming ...
Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools * Knowledge of chip level integration and ESD concepts a plus * Perl programming, TCL and SKILL programming ...
Toronto, ON · Hybrid
CA$100K - CA$500K/yr
You'll guide a top-tier team of Verification Engineers, shaping test strategies to validate ... Deep experience benchmarking on-chip networks under high-demand traffic, ensuring throughput ...
Toronto, ON · Hybrid
CA$100K - CA$500K/yr
You'll guide a top-tier team of Verification Engineers, shaping test strategies to validate ... Deep experience benchmarking on-chip networks under high-demand traffic, ensuring throughput ...
... engineering team. This will require a solid understanding of process technology, state of the art in chip design, and clear communication skills. You will represent the company externally at ...
... engineering team. This will require a solid understanding of process technology, state of the art in chip design, and clear communication skills. You will represent the company externally at ...
Ottawa, ON · Hybrid
CA$167K/yr
Medical
Dental
Vision
Life
Retirement
PTO
You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS ... You will lead efforts for a large block on a complex chip, mentor team members and track ...
Ottawa, ON · Hybrid
CA$167K/yr
Medical
Dental
Vision
Life
Retirement
PTO
You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS ... You will lead efforts for a large block on a complex chip, mentor team members and track ...
A Chip Design Engineer is responsible for designing and developing integrated circuits (ICs) used in electronic devices. They work with hardware description languages (HDLs) like Verilog or VHDL to create digital or analog circuit designs. Their role includes logic design, verification, simulation, and testing to ensure performance and power efficiency. They collaborate with teams across hardware, software, and manufacturing to bring chips from concept to production. Chip Design Engineers are essential in industries like consumer electronics, automotive, and telecommunications.
As a Chip Design Engineer, your daily tasks often include designing and simulating integrated circuits, reviewing schematics, writing and verifying code in hardware description languages, and collaborating closely with layout engineers and verification teams. You may also participate in design reviews, troubleshoot potential issues, and optimize chip performance to meet specific requirements. Working with cross-functional teams, including software engineers and product managers, is common to ensure the chip integrates seamlessly with end products. This role provides opportunities to see your designs progress from concept to final manufacturing, offering valuable hands-on experience at each stage of development.
To thrive as a Chip Design Engineer, you need a solid background in electrical engineering, digital and analog circuit design, and experience with VLSI principles, usually backed by a relevant degree. Proficiency with industry-standard tools like Cadence, Synopsys, and experience in HDL languages (such as Verilog or VHDL) is highly valued, as are certifications like Certified IC Designer. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set you apart. These competencies are critical for developing reliable, high-performance chips in a collaborative and deadline-driven environment.
For Chip Design Engineer jobs in Ontario, the most frequently searched job titles are:
The top searched job categories for Chip Design Engineer jobs in Ontario are:
CA$138K - CA$220K/yr
Full-time
Medical, Dental, Vision, Retirement, PTO
Re-posted 7 hours ago
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact.
Ciena'sWaveLogicfamily of products enables high-speed optical transmission solutions that are foundational to modern telecommunications networks. This role contributes to the continued advancement of high-speed circuit design for broadband fiber-optic systems within avibrant team with a proven track-record of success over 30 years of evolution in high-speed circuits for broadband fiber-optic modems - the team that pioneered the world's first high-speed DAC and ADC analog macros for coherent fiber-optic products.
We are looking for a hands-on Transmitter (Tx) SerDes DesignLeadto design and deliver our high-speed electrical transmitter macros for 224G and 448G SerDes in the latest deep-submicron CMOS technologies.
How you will make an impact:
Own schematic-level design and post-layout verification of the transmitter signal chain andit'sblocks:DAC-based output stage, serialization, clocking interface, and output driver
Work closely with management, system designers, and lab validation teams to evolve the architecture and meet standard and product requirements
Evaluate circuit topologies and recommend implementations based ontradeoffsacross power, area, bandwidth, and technology constraints.
Collaborate with layout and design engineers to deliver designs through full GDSII integration.
Drive extraction-based post-layout simulations andvalidatetransmitterperformance(bandwidth, linearity/RLM, return loss, jitter, and power)across process, voltage, and temperature conditions.
Own root-cause analysis of design- and post-layout performance gaps and implement the corrective design actions to meet specifications.
Maintain block- and transmitter-level performance and power tracking against the agreed targets.
Translate agreed architecture and system requirements into the transmitterimplementation, andfeed design and silicon learnings back to inform the next architecture step.
Build and use behavioral/design models (e.g., MATLAB, Verilog-A) to support topology tradeoffs and specification alignment.
Partner with lab validation teams to correlate silicon results with simulations and supporttest-chip,product bring-upand characterization.
Provide technical guidance and mentorship to more junior design and layout engineers, and report status and share experience with the group on a regular basis.
The must haves:
Education:Bachelor's degree in Electrical Engineering or Computer Engineering, or applicable scientific discipline.
Experience: 10+ years of industrial experience designing high-speed analog, mixed-signal, or SerDes transmitter circuits in advanced CMOS technologies, including schematic design through post-layout verification.
Application of transmitter circuit building blocks including DAC-based output stages, serializers or multiplexers, output drivers, and clocking circuits.
Execution of post-layout and extraction-based simulations tovalidateperformance across process, voltage, and temperature conditions.
Delivery of analog circuit designs through silicon validation.
Utilizationof Cadence, Mentor, or Synopsys tools including Virtuoso, Calibre, STAR-RC, and MMSIM.
Demonstrated written and verbal communication skills and ability to work independently and within a team environment.
Nice to haves:
Experience: Application of 224G or 448G PAM4 or PAM6 SerDes and related OIF-CEI or IEEE standards.
Experience contributing to transmitter architecture using MATLAB, Verilog-A, or C++.
Application of signal integrity, power integrity, channel, and package co-design methodologies, including use of EM tools such as HFSS or EMX.
Experience mentoring engineers within analog macro design teams.
Experience with mixed-signal validation using high-speed measurement and probing equipment.
Pay Range: The annual salary range for this position is $138,000 - $220,400 CAD.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is anEqual Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.
Sourced by ZipRecruiter
Telecommunications
5,001 - 10,000 Employees
Hanover, MD, US
1992
