Data Center Solutions Architect
OR · On-site +1
This role leads the development of standardized reference architectures and drives technical strategy across the full data-center thermal value chain-from chip to chiller. The Solutions Architect ...
OR · On-site +1
This role leads the development of standardized reference architectures and drives technical strategy across the full data-center thermal value chain-from chip to chiller. The Solutions Architect ...
OR · On-site +1
This role leads the development of standardized reference architectures and drives technical strategy across the full data-center thermal value chain-from chip to chiller. The Solutions Architect ...
Hillsboro, OR · On-site
$221 - $312/hr
Lead architecture definition and development of next‑generation high-speed IO PHYs with ... Create floorplans, extract chip parameters, and simulate analog behavior models to meet performance ...
New
Hillsboro, OR · On-site
$221 - $312/hr
Lead architecture definition and development of next‑generation high-speed IO PHYs with ... Create floorplans, extract chip parameters, and simulate analog behavior models to meet performance ...
New
$220K - $311K/yr
... chip parameters, and simulate analog behavior models to meet performance, power, and area goals ... with architecture and layout teams to design robust circuits with best-in-class electrical ...
$220K - $311K/yr
... chip parameters, and simulate analog behavior models to meet performance, power, and area goals ... with architecture and layout teams to design robust circuits with best-in-class electrical ...
OR · On-site +1
$63 - $83/hr
They will chip in both internally in their Community and externally in the marketplace. YOUR IMPACT: Responsibilities Salesforce Professional Services is looking for a Sr. Solution Architect with ...
OR · On-site +1
$63 - $83/hr
They will chip in both internally in their Community and externally in the marketplace. YOUR IMPACT: Responsibilities Salesforce Professional Services is looking for a Sr. Solution Architect with ...
Hillsboro, OR · On-site
$220K - $311K/yr
Lead architecture definition and development of next‑generation high-speed IO PHYs with ... Create floorplans, extract chip parameters, and simulate analog behavior models to meet performance ...
New
Hillsboro, OR · On-site
$220K - $311K/yr
Lead architecture definition and development of next‑generation high-speed IO PHYs with ... Create floorplans, extract chip parameters, and simulate analog behavior models to meet performance ...
New
Hillsboro, OR · On-site
$189K - $352K/yr
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PCIe Controller Architect and Technical Director to join our Silicon IP (SIP) team. Candidates will be ...
Hillsboro, OR · On-site
$189K - $352K/yr
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional PCIe Controller Architect and Technical Director to join our Silicon IP (SIP) team. Candidates will be ...
Hillsboro, OR · On-site
$164K - $311K/yr
Develop and drive analog and mixed-signal IP architectures, signal processing algorithms, and calibration algorithms for system-on-chip (SoC) independent AMS IPs. * Conduct top-down architectural ...
Hillsboro, OR · On-site
$164K - $311K/yr
Develop and drive analog and mixed-signal IP architectures, signal processing algorithms, and calibration algorithms for system-on-chip (SoC) independent AMS IPs. * Conduct top-down architectural ...
$141K - $145K/yr
In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
$141K - $145K/yr
In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
Beaverton, OR · On-site
$141K - $145K/yr
In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
Beaverton, OR · On-site
$141K - $145K/yr
In this role, we will be at the center of a PHY design effort working with architecture, CAD, ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...
Hillsboro, OR · Hybrid
Define the physical limits of what a chip can do, then break them! NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles ...
Hillsboro, OR · Hybrid
Define the physical limits of what a chip can do, then break them! NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles ...
$184K - $324K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic ...
$184K - $324K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic ...
$184K - $324K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic ...
$184K - $324K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic ...
$184K - $324K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic ...
$184K - $324K/yr
Generate block/chip level static timing constraints. Build full chip floor-plan including pin ... Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic ...
Beaverton, OR · On-site
Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block * Collaborate with other team members to integrate the block with the full chip * Use Verilog to design ...
Beaverton, OR · On-site
Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block * Collaborate with other team members to integrate the block with the full chip * Use Verilog to design ...
... and architects working on future product generations. * Develop comprehensive computation strategies spanning kernels for multichannel and multi-chip neural net implementations. Requirements:
Quick apply
... and architects working on future product generations. * Develop comprehensive computation strategies spanning kernels for multichannel and multi-chip neural net implementations. Requirements:
... off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure ...
... off-chip interconnect network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure ...
Hillsboro, OR · On-site
Drive the micro-architecture definition, feasibility studies and documentation of CPU sub-systems ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...
Hillsboro, OR · On-site
Drive the micro-architecture definition, feasibility studies and documentation of CPU sub-systems ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...
Hillsboro, OR · On-site
$140 - $220/hr
Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal ... This full-time position will allow the candidate to contribute to the architecture, design of next ...
Hillsboro, OR · On-site
$140 - $220/hr
Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal ... This full-time position will allow the candidate to contribute to the architecture, design of next ...
Drive the micro-architecture definition, feasibility studies and documentation of CPU sub-systems ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...
Drive the micro-architecture definition, feasibility studies and documentation of CPU sub-systems ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...
... chip designers to maintain clocking balance, resolve timing issues, and optimize power delivery and partitioning. - Partner with architecture, clocking design, and logic design teams to define and ...
... chip designers to maintain clocking balance, resolve timing issues, and optimize power delivery and partitioning. - Partner with architecture, clocking design, and logic design teams to define and ...
$49.2K - $64.1K
3% of jobs
$64.1K - $79K
4% of jobs
$79K - $93.9K
17% of jobs
$94.8K is the 25th percentile. Wages below this are outliers.
$93.9K - $108.8K
17% of jobs
The median wage is $120.9K / yr.
$108.8K - $123.7K
11% of jobs
$123.7K - $138.6K
4% of jobs
$138.6K - $153.5K
4% of jobs
$153.5K - $168.3K
3% of jobs
$173.5K is the 75th percentile. Wages above this are outliers.
$168.3K - $183.2K
33% of jobs
$183.2K - $198.1K
1% of jobs
$198.1K - $213K
2% of jobs
$49.2K
$136.1K
$213K
| Aspect | Chip Architect | Hardware Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; experience in chip design and architecture | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; focus on circuit design and implementation |
| Work Environment | Design teams, R&D labs, collaborative project settings | Design labs, testing facilities, manufacturing environments |
| Employer & Industry Usage | Semiconductor companies, tech firms, integrated circuit manufacturers | Electronics companies, semiconductor firms, hardware development labs |
The main difference is that a Chip Architect focuses on designing the overall architecture and high-level specifications of chips, while a Hardware Design Engineer concentrates on implementing circuit designs based on specifications. Both roles require electrical engineering expertise, but the Chip Architect is more involved in conceptual and architectural decisions, whereas the Hardware Design Engineer handles detailed circuit development and testing.
For Chip Architect jobs in Oregon, the most frequently searched job titles are:
The top searched job categories for Chip Architect jobs in Oregon are:
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Position Summary
The Solutions Architect is a senior technical leader within Daikin Applied's Data Center of Excellence (CoE). This role leads the development of standardized reference architectures and drives technical strategy across the full data-center thermal value chain-from chip to chiller.
The Solutions Architect will have direct customer engagement and work closely with data center owners, developers, hyperscalers, integrators, and Neo-Cloud operators to shape design standards, influence solution selection, and guide purchasing decisions aligned with Daikin Data Center Solutions.
This is a highly visible role that blends engineering depth with commercial impact. This role directly enhances Daikin's competitive position by strengthening market credibility and customer trust with bestinclass technical engagement and increasing design wins through direct customer influence. Reducing technical and commercial risk via validated architectures and PoC testing. Accelerating product innovation through realworld performance insights and solution leadership.
Essential Duties and Responsibilities
Preferred Knowledge, Skills, and Abilities
Required Knowledge, Skills, and Abilities
Benefits
Daikin Applied offers the following benefits for this position, subject to applicable eligibility requirements:
The typical annual base salary for this position ranges from 146,900K - 246,200K. The range displayed represents the pay range for all positions in the job grade which this position falls. Individual base pay will depend on a wide range of factors including your skills, qualifications, experience, and location.
If you're looking for an engaging career with growth opportunities in a supportive environment, you'll love a career at Daikin Applied!