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Cadence Spectre Jobs (NOW HIRING)

Apple

Timing Radio Integration Engineer

Irvine, CA · On-site

$111K - $150K/yr

Experience with Cadence Spectre analog design tools for running analog simulations as needed. MSEE with extensive experience for top radio level timing and digital verification. Digital Power ...

Neuralink

Software Engineer, ASIC

South San Francisco, CA · On-site

$123K - $216K/yr

Cadence Virtuoso, Cadence Spectre * Terraform, Ansible, Packer, MAAS * Bazel and Nix * Prometheus, ClickHouse, Grafana * Ray, Docker, Kubernetes * AWS, OCI (Oracle Cloud Infrastructure) * RHEL ...

Neuralink

Software Engineer, ASIC

Austin, TX

$123K - $216K/yr

Cadence Virtuoso, Cadence Spectre * Terraform, Ansible, Packer, MAAS * Bazel and Nix * Prometheus, ClickHouse, Grafana * Ray, Docker, Kubernetes * AWS, OCI (Oracle Cloud Infrastructure) * RHEL ...

NXP Semiconductors

Systems IC Architect

Austin, TX

$240K/yr

Proficiency in circuit simulation tools (e.g., Cadence Spectre, PSPICE, HSPICE, Saber, Simetrix/Simplis, Verilog-AMS) and knowledge of PCB materials and stack-up. * Experience in Powering high ...

NXP Semiconductors

Systems IC Architect

San Jose, CA

$284K/yr

Proficiency in circuit simulation tools (e.g., Cadence Spectre, PSPICE, HSPICE, Saber, Simetrix/Simplis, Verilog-AMS) and knowledge of PCB materials and stack-up. * Experience in Powering high ...

NXP Semiconductors N.V.

Systems IC Architect

Austin, TX · On-site

$240K/yr

Proficiency in circuit simulation tools (e.g., Cadence Spectre, PSPICE, HSPICE, Saber, Simetrix/Simplis, Verilog-AMS) and knowledge of PCB materials and stack-up. * Experience in Powering high ...

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All JobsCadence Spectre Jobs

Cadence Spectre information

See salary details

$120.5K

$162.4K

$187.5K

How much do cadence spectre jobs pay per year?

As of Jun 10, 2026, the average yearly pay for cadence spectre in the United States is $162,359.00, according to ZipRecruiter salary data. Most workers in this role earn between $151,000.00 and $176,000.00 per year, depending on experience, location, and employer.

What is the difference between Cadence Spectre vs Cadence Virtuoso?

FeatureCadence SpectreCadence Virtuoso
Primary UseAnalog and RF circuit simulationAnalog, digital, and mixed-signal design environment
Work EnvironmentSimulation and verificationDesign and layout editing
Required SkillsSPICE modeling, circuit analysisDesign schematic, layout, verification

Cadence Spectre is primarily used for circuit simulation, focusing on analog and RF performance analysis. Cadence Virtuoso is a comprehensive design platform for creating and editing circuit schematics and layouts. While Spectre handles simulation tasks, Virtuoso manages the overall design process. Both tools are integral in the IC design flow, often used together for efficient circuit development and verification.

What is Cadence Spectre?

Cadence Spectre is a powerful circuit simulator used for designing and verifying analog, RF, and mixed-signal integrated circuits. It is part of the Cadence Virtuoso Design Environment and offers accurate SPICE-level simulation capabilities. Engineers use Spectre to analyze circuit behavior, optimize performance, and ensure reliability before manufacturing chips. This tool supports a range of analyses, including DC, AC, transient, noise, and more, making it essential for advanced semiconductor design.

What are the key skills and qualifications needed to thrive as a Cadence Spectre engineer, and why are they important?

To excel as a Cadence Spectre engineer, a strong background in electrical engineering, circuit simulation, and analog/mixed-signal design is essential, typically supported by a relevant degree or equivalent experience. Proficiency in using the Cadence Spectre simulation tool, SPICE modeling, and scripting languages like SKILL or Python is highly valued. Strong problem-solving abilities, attention to detail, and effective communication skills help engineers collaborate and troubleshoot complex circuit issues efficiently. These competencies are vital for ensuring accurate simulation results and driving successful chip design and verification projects.

What are some common challenges faced by engineers working with Cadence Spectre, and how can they be overcome?

Engineers using Cadence Spectre often encounter challenges related to simulation performance and convergence, especially when working with large or complex analog/mixed-signal circuits. To address these, it’s important to optimize circuit netlists, use appropriate simulation settings, and leverage Spectre’s advanced debugging tools. Collaborating closely with design and verification teams can also help identify and resolve modeling or configuration issues more efficiently. Continuous learning and staying updated on new Spectre features can further improve productivity and simulation accuracy.
Infographic showing various Cadence Spectre job openings in the United States as of June 2026, with employment types broken down into 20% Full Time, 40% Part Time, and 40% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $162,359 per year, or $78.1 per hour.
Senior Analog/Mixed-Signal Design Engineer

Senior Analog/Mixed-Signal Design Engineer

Alphacore Inc

Arizona, LA • On-site

$193K/yr

Full-time

Posted 10 days ago

Job description

Position: Senior Analog/Mixed-Signal Design Engineer

What You'll Do :-

As a Senior Analog/Mixed-Signal Design Engineer, you will take a lead role in the design and development of high-performance analog and mixed-signal integrated circuits, with a strong emphasis on high-speed and high-resolution data converters. You will independently own key design blocks, drive performance optimization, collaborate closely with layout, verification, and system teams, and contribute to silicon bring-up and product maturation.
Your Responsibilities :-

Lead the design, simulation, and implementation of analog/mixed-signal circuit blocks.
Contribute to high-speed ADC architecture evaluation, performance modeling, and design trade-off analysis.
Work closely with layout engineers to guide layout floorplan, matching strategy, and parasitic-aware optimization.
Perform transistor-level simulations, corner/Monte-Carlo analysis, stability/noise/jitter analysis, and document detailed design results.
Support silicon bring-up, debug performance issues, and collaborate on validation and characterization.
Improve internal design methodologies, modeling flows, and reusable IP libraries.

What We're Looking For :-

Master's degree in Electrical/Electronics Engineering with 5+ years and Ph.D. with 2+ years of relevant industry experience.
Strong knowledge of analog and mixed-signal design fundamentals (noise, matching, dynamic range, stability, clocking, device physics, etc.).
Proven hands-on experience with high-speed (>10 GS/s) or high-resolution (>14-bit) ADC/DAC development.
Proficiency with Cadence/Spectre or equivalent SPICE simulation environments.
Experience working with layout teams and understanding layout-dependent effects and parasitics.
Strong problem-solving, analytical debugging skills, and ability to own designs independently.
Excellent communication skills and ability to collaborate in a team-based environment.

Nice to Have :-

Experience in post-silicon validation and lab debug.
Scripting skills (Python/Matlab) and data analysis.
Experience with advanced CMOS nodes.
Employment Type: FULL_TIME

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